Searched refs:rsubhn (Results 1 – 17 of 17) sorted by relevance
66 ;CHECK: rsubhn.8b69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)75 ;CHECK: rsubhn.4h78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)84 ;CHECK: rsubhn.2s87 %tmp3 = call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)93 ;CHECK: rsubhn.8b95 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwi…96 …%vrsubhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b) n…103 ;CHECK: rsubhn.4h[all …]
111 ; CHECK: rsubhn.8b v0, v0, v1114 …%vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) noun…115 …%vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) no…144 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
41 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>)43 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>)45 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>)955 ; CHECK: rsubhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h957 %vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b)963 ; CHECK: rsubhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s965 %vrsubhn2.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b)971 ; CHECK: rsubhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d973 %vrsubhn2.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b)979 ; CHECK: rsubhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h[all …]
401 rsubhn v0.8b, v1.8h, v2.8h402 rsubhn v0.4h, v1.4s, v2.4s403 rsubhn v0.2s, v1.2d, v2.2d
2819 rsubhn v0.8b, v1.8h, v2.8b2820 rsubhn v0.4h, v1.4s, v2.4h2821 rsubhn v0.2s, v1.2d, v2.2s
1458 # CHECK: rsubhn v0.8b, v1.8h, v2.8h1459 # CHECK: rsubhn v0.4h, v1.4s, v2.4s1460 # CHECK: rsubhn v0.2s, v1.2d, v2.2d
2734 GEN_BINARY_TEST(rsubhn, 2s, 2d, 2d)2736 GEN_BINARY_TEST(rsubhn, 4h, 4s, 4s)2738 GEN_BINARY_TEST(rsubhn, 8b, 8h, 8h)
26965 rsubhn v9.2s, v7.2d, v8.2d 05349f4ad2ee4133e08c964a68b6e61b d104a604b0404d63161107838b952a99 000…26967 rsubhn v9.4h, v7.4s, v8.4s 50ee42785838efb6f9983ba9b3a2dbfd 32e86dc600fde27927fcc446d6ce3061 000…26969 rsubhn v9.8b, v7.8h, v8.8h 79526b3762c87e9a13f68777f17941ba b3cdbec4fee108e3cc21fd348f622409 000…
2158 V(rsubhn) \
2153 V(rsubhn, Rsubhn) \
3587 void rsubhn(const VRegister& vd,
2749 case NEON_RSUBHN: rsubhn(vf, rd, rn, rm); break; in VisitNEON3Different()
3373 LogicVRegister Simulator::rsubhn(VectorFormat vform, in rsubhn() function in vixl::Simulator
2449 V(rsubhn, NEON_RSUBHN, vd.IsD()) \
3846 DEFINE_TEST_NEON_3DIFF_NARROW(rsubhn, Basic)
2928 void rsubhn(const VRegister& vd,
3427 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;