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Searched refs:s_load_dword (Results 1 – 25 of 56) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dllvm.r600.read.local.size.ll10 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x6
11 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18
12 ; CI-HSA: s_load_dword [[XY:s[0-9]+]], s[4:5], 0x1
13 ; VI-HSA: s_load_dword [[XY:s[0-9]+]], s[4:5], 0x4
28 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x7
29 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c
43 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
44 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x20
55 ; SI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x6
56 ; SI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x7
[all …]
Duse-sgpr-multiple-times.ll11 ; GCN: s_load_dword [[SGPR:s[0-9]+]],
21 ; GCN: s_load_dword [[SGPR:s[0-9]+]],
31 ; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
32 ; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
33 ; VI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
34 ; VI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
45 ; GCN-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
46 ; GCN-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0xc|0x30}}
71 ; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
72 ; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
[all …]
Datomic_cmp_swap_local.ll7 ; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
8 ; SICI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
9 ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
10 ; VI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
26 ; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
28 ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
59 ; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
60 ; SICI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xa
61 ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
62 ; VI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x28
[all …]
Dllvm.AMDGPU.div_fixup.ll8 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
9 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
10 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
11 ; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
12 ; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34
13 ; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
Doperand-spacing.ll7 ; SI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
8 ; SI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
9 ; VI-DAG: s_load_dword [[SREGA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
10 ; VI-DAG: s_load_dword [[SREGB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
Dllvm.AMDGPU.div_fmas.ll11 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
12 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
13 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
14 ; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
15 ; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34
16 ; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
30 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
31 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
44 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
45 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
[all …]
Dsmrd.ll7 ; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
8 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4
19 ; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}
20 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
32 ; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
33 ; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
34 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
62 ; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
63 ; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
64 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
[all …]
Dwork-item-intrinsics.ll28 ; GCN-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0
43 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1
44 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
58 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2
59 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
73 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x3
74 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc
88 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
89 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x10
103 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x5
[all …]
Dllvm.AMDGPU.read.workdim.ll9 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
10 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
21 ; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
22 ; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
Dllvm.AMDGPU.clamp.ll10 ; SI: s_load_dword [[ARG:s[0-9]+]],
23 ; SI: s_load_dword [[ARG:s[0-9]+]],
35 ; SI: s_load_dword [[ARG:s[0-9]+]],
47 ; SI: s_load_dword [[ARG:s[0-9]+]],
60 ; SI: s_load_dword [[ARG:s[0-9]+]],
Dkernel-args.ll8 ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
9 ; VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
21 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
22 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
33 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
34 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
45 ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
46 ; VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
58 ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb
59 ; VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
[all …]
Dno-shrink-extloads.ll10 ; SI: s_load_dword s
35 ; SI: s_load_dword s
57 ; SI: s_load_dword s
79 ; SI: s_load_dword s
101 ; SI: s_load_dword s
126 ; SI: s_load_dword s
148 ; SI: s_load_dword s
172 ; SI: s_load_dword s
194 ; SI: s_load_dword [[LOAD:s[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0x0
Dfcopysign.f32.ll12 ; SI: s_load_dword [[SMAG:s[0-9]+]], {{.*}} 0xb
13 ; SI: s_load_dword [[SSIGN:s[0-9]+]], {{.*}} 0xc
14 ; VI: s_load_dword [[SMAG:s[0-9]+]], {{.*}} 0x2c
15 ; VI: s_load_dword [[SSIGN:s[0-9]+]], {{.*}} 0x30
Dimm.ll130 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
140 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
150 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
160 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
170 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
180 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
190 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
200 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
210 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
242 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
[all …]
Dsetcc-opt.ll127 ; SI-DAG: s_load_dword [[A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
128 ; SI-DAG: s_load_dword [[B:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
129 ; VI-DAG: s_load_dword [[A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
130 ; VI-DAG: s_load_dword [[B:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
145 ; SI: s_load_dword [[VALUE:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
146 ; VI: s_load_dword [[VALUE:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
176 ; GCN: s_load_dword [[B:s[0-9]+]]
193 ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
194 ; VI: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
Dllvm.AMDGPU.class.ll10 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
11 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
25 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
26 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
41 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
42 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
57 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
58 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
74 ; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
87 ; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
[all …]
Dcgp-addressing-modes.ll231 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x7{{$}}
259 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0xff{{$}}
291 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}}
322 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
352 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
377 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}}
379 ; CI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x3ffff{{$}}
380 ; VI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0xffffc{{$}}
412 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}}
414 ; CI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x40000{{$}}
[all …]
Dschedule-kernel-arg-loads.ll7 ; SI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
8 ; SI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xe
13 ; VI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
15 ; VI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x38
Dfabs.ll75 ; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
76 ; VI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
87 ; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
88 ; VI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
Dshl_add_constant.ll57 ; SI-DAG: s_load_dword [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
58 ; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
73 ; SI-DAG: s_load_dword [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
74 ; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
Dgv-const-addrspace.ll11 ; GCN: s_load_dword
32 ; GCN: s_load_dword
55 ; GCN: s_load_dword
70 ; GCN: s_load_dword
Dmul.ll44 ; SI: s_load_dword
45 ; SI: s_load_dword
56 ; SI: s_load_dword
57 ; SI: s_load_dword
111 ; SI: s_load_dword [[SRC0:s[0-9]+]],
112 ; SI: s_load_dword [[SRC1:s[0-9]+]],
Dtrunc-store-i1.ll6 ; SI: s_load_dword [[LOAD:s[0-9]+]],
25 ; SI: s_load_dword [[LOAD:s[0-9]+]],
Dinline-constraints.ll8 ; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}]
18 %s32 = tail call i32 asm sideeffect "s_load_dword $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
/external/llvm/test/MC/AMDGPU/
Dsmrd.s11 s_load_dword s1, s[2:3], 0xfc label
14 s_load_dword s1, s[2:3], 0xff label
17 s_load_dword s1, s[2:3], 0x100 label
25 s_load_dword s1, s[2:3], 1 label
28 s_load_dword s1, s[2:3], s4 label

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