| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vecFold.ll | 10 ; CHECK-NEXT: shrn2.16b v0, v1, #5
26 ; CHECK-NEXT: shrn2.8h v0, v1, #5
42 ; CHECK-NEXT: shrn2.4s v0, v1, #5
71 ; CHECK-NEXT: shrn2.8h v0, v2, #5
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| D | neon-diagnostics.ll | 16 ; CHECK-NOT: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #35
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| D | arm64-neon-simd-shift.ll | 263 ; CHECK: shrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
275 ; CHECK: shrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
287 ; CHECK: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
299 ; CHECK: shrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
311 ; CHECK: shrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
323 ; CHECK: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
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| D | arm64-vshift.ll | 706 ;CHECK: shrn2.16b v0, {{v[0-9]+}}, #1
717 ;CHECK: shrn2.8h v0, {{v[0-9]+}}, #1
728 ;CHECK: shrn2.4s v0, {{v[0-9]+}}, #1
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| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-shift.s | 265 shrn2 v0.16b, v1.8h, #3
266 shrn2 v0.8h, v1.4s, #3
267 shrn2 v0.4s, v1.2d, #3
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| D | arm64-advsimd.s | 1474 shrn2.16b v0, v0, #2
1476 shrn2.8h v0, v0, #4
1478 shrn2.4s v0, v0, #6
1646 ; CHECK: shrn2.16b v0, v0, #2 ; encoding: [0x00,0x84,0x0e,0x4f]
1648 ; CHECK: shrn2.8h v0, v0, #4 ; encoding: [0x00,0x84,0x1c,0x4f]
1650 ; CHECK: shrn2.4s v0, v0, #6 ; encoding: [0x00,0x84,0x3a,0x4f]
1806 shrn2 v8.16b, v9.8h, #2
1808 shrn2 v6.8h, v7.4s, #4
1810 shrn2 v4.4s, v5.2d, #6
1876 ; CHECK: shrn2.16b v8, v9, #2 ; encoding: [0x28,0x85,0x0e,0x4f]
[all …]
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| D | neon-diagnostics.s | 1810 shrn2 v0.16b, v1.8h, #17
1811 shrn2 v0.8h, v1.4s, #33
1812 shrn2 v0.4s, v1.2d, #65
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| /external/libavc/common/armv8/ |
| D | ih264_resi_trans_quant_av8.s | 568 shrn2 v0.8h, v23.4s, #1 //i4_value = (x3 + x2) >> 1;
570 shrn2 v1.8h, v25.4s, #1 //i4_value = (x3 - x2) >> 1;
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| /external/vixl/src/vixl/a64/ |
| D | logic-a64.cc | 2507 LogicVRegister Simulator::shrn2(VectorFormat vform, in shrn2() function in vixl::Simulator
2669 return shrn2(vform, dst, src, shift).UnsignedSaturate(vform); in uqshrn2()
3324 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in addhn2()
3368 shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in subhn2()
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| D | simulator-a64.h | 2082 LogicVRegister shrn2(VectorFormat vform,
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| D | macro-assembler-a64.h | 2404 V(shrn2, Shrn2) \
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| D | assembler-a64.h | 3302 void shrn2(const VRegister& vd,
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| D | simulator-a64.cc | 3762 shrn2(vf, rd, rn, right_shift); in VisitNEONShiftImmediate()
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| D | assembler-a64.cc | 4395 void Assembler::shrn2(const VRegister& vd, in shrn2() function in vixl::Assembler
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 2049 # CHECK: shrn2.16b v0, v0, #6
2051 # CHECK: shrn2.8h v0, v0, #12
2053 # CHECK: shrn2.4s v0, v0, #26
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| D | neon-instructions.txt | 957 # CHECK: shrn2 v0.16b, v1.8h, #3
958 # CHECK: shrn2 v0.8h, v1.4s, #3
959 # CHECK: shrn2 v0.4s, v1.2d, #3
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| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 27479 shrn2 v4.4s, v29.2d, #1 05a003fc900f175872e9f9c702e3af02 47b46e2da3006c22acb82c8f0707bcd1 d180…
27480 shrn2 v4.4s, v29.2d, #32 ce9d16cc51acf288c7fa0a9e80db4e19 e6577d7b0cd1336853c02e8cdb72ea16 e65…
27483 shrn2 v4.8h, v29.4s, #1 37dd74eff68b2b92750df7e73f159295 37d4bb79ebe9d590c97f9f3d4de279ea 5dbc…
27484 shrn2 v4.8h, v29.4s, #16 63d3f58415774aa77a78bbbb98ac6a3a bf4ecdb9d7061609e6002aa6612a564c bf4…
27487 shrn2 v4.16b, v29.8h, #1 5c2be056dd758c1dfb879d9518351b70 05a56feb04e721cba2ccf63cd0e241d7 d2f5…
27488 shrn2 v4.16b, v29.8h, #8 d2d9c4bfdf8d8646d64b49b512890211 dc35fbad7baef126dc43bfdf6ba52443 dcfb…
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| /external/vixl/doc/ |
| D | supported-instructions.md | 3119 void shrn2(const VRegister& vd,
|