| /external/llvm/test/MC/AMDGPU/ |
| D | flat.s | 23 flat_load_dword v1, v[3:4] glc slc
31 flat_load_dword v1, v[3:4] glc slc tfe
35 flat_load_dword v1, v[3:4] glc tfe slc
39 flat_load_dword v1, v[3:4] slc
43 flat_load_dword v1, v[3:4] slc glc
47 flat_load_dword v1, v[3:4] slc tfe
51 flat_load_dword v1, v[3:4] slc glc tfe
55 flat_load_dword v1, v[3:4] slc tfe glc
67 flat_load_dword v1, v[3:4] tfe slc
71 flat_load_dword v1, v[3:4] tfe glc slc
[all …]
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| D | mubuf.s | 25 buffer_load_dword v1, s[4:7], s1 offset:4 slc
34 buffer_load_dword v1, s[4:7], s1 offset:4 glc tfe slc
37 buffer_load_dword v1, s[4:7], s1 glc tfe slc offset:4
53 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 slc
62 buffer_load_dword v1, v2, s[4:7], s1 offen offset:4 glc tfe slc
65 buffer_load_dword v1, v2, s[4:7], s1 offen glc tfe slc offset:4
81 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc
90 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc tfe slc
93 buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe slc offset:4
109 buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc
[all …]
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.SI.load.dword.ll | 10 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 glc slc
11 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc slc
12 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen glc slc
13 …uffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen glc slc
15 …{{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, [[K]] idxen offen offset:65535 glc slc
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.td | 114 SDTCisVT<11, i32>, // slc(imm)
526 def slc : slc_base <SLCMubufMatchClass>;
2238 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2240 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2252 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2254 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2298 bits<1> slc;
2388 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2389 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2395 slc:$slc),
[all …]
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| D | VIInstrFormats.td | 43 bits<1> slc;
52 let Inst{17} = slc;
72 bits<1> slc;
87 let Inst{54} = slc;
|
| D | SIIntrinsics.td | 37 llvm_i32_ty, // slc(imm)
51 llvm_i32_ty, // slc(imm)
68 llvm_i32_ty, // slc(imm)
83 llvm_i32_ty, // slc(imm)
|
| D | SIInstrFormats.td | 467 bits<1> slc;
482 let Inst{54} = slc;
498 bits<1> slc;
514 let Inst{54} = slc;
528 bits<1> slc;
541 let Inst{25} = slc;
553 bits<1> slc;
559 let Inst{17} = slc;
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| D | SIInstructions.td | 2223 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2225 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2240 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2242 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2912 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))),
2913 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe)
2944 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2947 (as_i1imm $slc), (as_i1imm $tfe))
2952 imm:$offset, 1, 0, imm:$glc, imm:$slc,
2954 (offen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
[all …]
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| D | SIInstrInfo.cpp | 2189 MIB.addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc)); in legalizeOperands()
2209 .addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc)) in legalizeOperands()
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| /external/icu/icu4c/source/data/unidata/ |
| D | ppucd.txt | 93 property;String;slc;Simple_Lowercase_Mapping
1105 …t>;NFKC_QC=Y;NFKD_QC=Y;nt=None;SB=XX;sc=Zzzz;scf=<code point>;scx=<script>;slc=<code point>;stc=<c…
1179 …;Hex;IDC;IDS;na=LATIN CAPITAL LETTER A;NFKC_CF=0061;SB=UP;sc=Latn;scf=0061;slc=0061;Upper;WB=LE;XI…
1180 …;Hex;IDC;IDS;na=LATIN CAPITAL LETTER B;NFKC_CF=0062;SB=UP;sc=Latn;scf=0062;slc=0062;Upper;WB=LE;XI…
1181 …;Hex;IDC;IDS;na=LATIN CAPITAL LETTER C;NFKC_CF=0063;SB=UP;sc=Latn;scf=0063;slc=0063;Upper;WB=LE;XI…
1182 …;Hex;IDC;IDS;na=LATIN CAPITAL LETTER D;NFKC_CF=0064;SB=UP;sc=Latn;scf=0064;slc=0064;Upper;WB=LE;XI…
1183 …;Hex;IDC;IDS;na=LATIN CAPITAL LETTER E;NFKC_CF=0065;SB=UP;sc=Latn;scf=0065;slc=0065;Upper;WB=LE;XI…
1184 …;Hex;IDC;IDS;na=LATIN CAPITAL LETTER F;NFKC_CF=0066;SB=UP;sc=Latn;scf=0066;slc=0066;Upper;WB=LE;XI…
1185 …c=Lu;IDC;IDS;na=LATIN CAPITAL LETTER G;NFKC_CF=0067;SB=UP;sc=Latn;scf=0067;slc=0067;Upper;WB=LE;XI…
1186 …c=Lu;IDC;IDS;na=LATIN CAPITAL LETTER H;NFKC_CF=0068;SB=UP;sc=Latn;scf=0068;slc=0068;Upper;WB=LE;XI…
[all …]
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| D | changes.txt | 209 when there is an slc mapping but no scf
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| /external/icu/icu4c/source/tools/toolutil/ |
| D | ppucd.cpp | 43 scf(U_SENTINEL), slc(U_SENTINEL), stc(U_SENTINEL), suc(U_SENTINEL), in UniProps()
364 props.slc=U_SENTINEL; in parseProperty()
421 props.slc=parseCodePoint(v, errorCode); in parseProperty()
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| D | ppucd.h | 52 UChar32 scf, slc, stc, suc; member
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIInstrInfo.td | 448 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_128:$vaddr,
458 i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
470 i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
481 GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
|
| /external/jetty/src/java/org/eclipse/jetty/xml/ |
| D | XmlConfiguration.java | 95 Class<?> slc = ClassLoader.getSystemClassLoader().loadClass("java.util.ServiceLoader");
96 Method load = slc.getMethod("load",Class.class);
|
| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/ |
| D | org.eclipse.ui.workbench_3.6.1.M20101117-0800.jar | META-INF/MANIFEST.MF
META-INF/ECLIPSEF.SF
META-INF/ECLIPSEF ... |
| /external/icu/icu4c/source/data/misc/ |
| D | supplementalData.txt | 6221 "slc~j",
|
| /external/dagger2/lib/ |
| D | auto-value-1.0.jar | META-INF/
META-INF/MANIFEST.MF
com/
com/google/
com/ ... |