| /external/opencv3/modules/features2d/src/kaze/ |
| D | KAZEConfig.h | 24 , soffset(1.60f) in KAZEOptions()
40 float soffset; member
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| D | AKAZEConfig.h | 22 , soffset(1.6f) in AKAZEOptions()
45 float soffset; ///< Base scale offset (sigma units) member
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| D | KAZEFeatures.cpp | 69 … aux.esigma = options_.soffset*pow((float)2.0f, (float)(j) / (float)(options_.nsublevels)+i); in Allocate_Memory_Evolution()
104 gaussian_2D_convolution(evolution_[0].Lt, evolution_[0].Lt, 0, 0, options_.soffset); in Create_Nonlinear_Scale_Space()
471 kpts_[i].size = 2.0f*options_.soffset*pow((float)2.0f, dsc); in Do_Subpixel_Refinement()
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| D | AKAZEFeatures.cpp | 72 step.esigma = options_.soffset*pow(2.f, (float)(j) / (float)(options_.nsublevels) + i); in Allocate_Memory_Evolution()
106 gaussian_2D_convolution(evolution_[0].Lt, evolution_[0].Lt, 0, 0, options_.soffset); in Create_Nonlinear_Scale_Space()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | VIInstrFormats.td | 45 bits<8> soffset;
59 let Inst{63-56} = soffset;
74 bits<8> soffset;
89 let Inst{63-56} = soffset;
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| D | SIInstrInfo.td | 107 SDTCisVT<4, i32>, // soffset(SGPR)
2238 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2240 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2252 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2254 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2300 bits<8> soffset;
2388 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2389 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2394 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2396 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
[all …]
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| D | SIIntrinsics.td | 30 llvm_i32_ty, // soffset(SGPR)
46 llvm_i32_ty, // soffset(SGPR)
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| D | SIInstrFormats.td | 469 bits<8> soffset;
484 let Inst{63-56} = soffset;
500 bits<8> soffset;
516 let Inst{63-56} = soffset;
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| D | SIInstructions.td | 2911 (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2913 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe)
2926 i32:$soffset, u16imm:$offset))),
2927 (Instr $vaddr, $srsrc, $soffset, $offset, 0, 0, 0)
2943 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
2946 (offset $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
2951 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2954 (offen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
2959 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2962 (idxen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
[all …]
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| D | SIInstrInfo.cpp | 159 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) || in areLoadsFromSameBasePtr()
260 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1) in getMemOpBaseRegImmOfs()
2163 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset); in legalizeOperands()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIInstrInfo.td | 459 i1imm:$tfe, SReg_32:$soffset),
470 i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
481 GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | mubuf.ll | 71 ; the soffset operand.
|
| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/ |
| D | com.ibm.icu_4.2.1.v20100412.jar | META-INF/MANIFEST.MF
META-INF/ECLIPSEF.SF
META-INF/ECLIPSEF ... |
| D | org.apache.commons.httpclient_3.1.0.v201005080502.jar | META-INF/MANIFEST.MF
META-INF/ECLIPSEF.SF
META-INF/ECLIPSEF ... |