splat (reference) in projects: external

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Searched refs:splat (Results 1 – 25 of 76) sorted by relevance

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/external/llvm/test/CodeGen/SystemZ/
D	vec-perm-01.ll	1 ; Test vector splat. 5 ; Test v16i8 splat of the first element. 15 ; Test v16i8 splat of the last element. 28 ; Test v16i8 splat of an arbitrary element, using the second operand of 42 ; Test v8i16 splat of the first element. 52 ; Test v8i16 splat of the last element. 63 ; Test v8i16 splat of an arbitrary element, using the second operand of 75 ; Test v4i32 splat of the first element. 85 ; Test v4i32 splat of the last element. 95 ; Test v4i32 splat of an arbitrary element, using the second operand of [all …]
D	vec-perm-02.ll	5 ; Test v16i8 splat of the first element. 17 ; Test v16i8 splat of the last element. 32 ; Test v16i8 splat of an arbitrary element, using the second operand of 48 ; Test v8i16 splat of the first element. 60 ; Test v8i16 splat of the last element. 73 ; Test v8i16 splat of an arbitrary element, using the second operand of 87 ; Test v4i32 splat of the first element. 99 ; Test v4i32 splat of the last element. 111 ; Test v4i32 splat of an arbitrary element, using the second operand of 124 ; Test v2i64 splat of the first element. [all …]
D	vec-combine-01.ll	`43 ; ...and again in a case where there's also a splat and a bitcast. 53 %splat = shufflevector <2 x i64> %v3, <2 x i64> undef, 55 %splatcast = bitcast <2 x i64> %splat to <4 x i32> 75 %splat = shufflevector <2 x i64> %v3, <2 x i64> undef, 77 %splatcast = bitcast <2 x i64> %splat to <4 x i32> 97 %splat = shufflevector <2 x i64> %v3, <2 x i64> undef, 99 %splatcast = bitcast <2 x i64> %splat to <4 x i32>`
/external/llvm/test/CodeGen/Mips/msa/
D	3r_splat.ll	1 ; Test the MSA splat intrinsics that are encoded with the 3R instruction 15 %1 = tail call <16 x i8> @llvm.mips.splat.b(<16 x i8> %0, i32 %a) 20 declare <16 x i8> @llvm.mips.splat.b(<16 x i8>, i32) nounwind 26 ; MIPS32-DAG: splat.b [[R4:\$w[0-9]+]], [[R3]][$4] 36 %1 = tail call <8 x i16> @llvm.mips.splat.h(<8 x i16> %0, i32 %a) 41 declare <8 x i16> @llvm.mips.splat.h(<8 x i16>, i32) nounwind 47 ; MIPS32-DAG: splat.h [[R4:\$w[0-9]+]], [[R3]][$4] 57 %1 = tail call <4 x i32> @llvm.mips.splat.w(<4 x i32> %0, i32 %a) 62 declare <4 x i32> @llvm.mips.splat.w(<4 x i32>, i32) nounwind 68 ; MIPS32-DAG: splat.w [[R4:\$w[0-9]+]], [[R3]][$4] [all …]
D	llvm-stress-s2501752154-simplified.ll	`9 ; splat, but then proceeded to legalize the undef's to zero, leaving it as a 10 ; non-splat that cannot be selected. It should have eliminated the undef's by 11 ; rewriting the splat constant.`
D	llvm-stress-s449609655-simplified.ll	`11 ; isVSplat() returned the splat value for <i8 -1, i8 -1, ...> as a 32-bit APInt 12 ; (255), but the zeroinitializer splat value as an 8-bit APInt (0). The`
D	llvm-stress-s2090927243-simplified.ll	`8 ; splat, but are legalized to zero if left in the DAG which changes the constant 9 ; into a non-splat.`
/external/llvm/test/CodeGen/X86/
D	avx2-vbroadcast.ll	628 ; These tests check that a vbroadcast instruction is used when we have a splat 705 %splat.splatinsert = insertelement <16 x i8> undef, i8 %tmp2, i32 0 706 …%splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitial… 707 %tmp3 = bitcast <16 x i8> %splat.splat to <2 x i64> 724 %splat.splatinsert = insertelement <32 x i8> undef, i8 %tmp2, i32 0 725 …%splat.splat = shufflevector <32 x i8> %splat.splatinsert, <32 x i8> undef, <32 x i32> zeroinitial… 726 %tmp3 = bitcast <32 x i8> %splat.splat to <4 x i64> 743 %splat.splatinsert = insertelement <8 x i16> undef, i16 %tmp2, i32 0 744 …%splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitiali… 745 %tmp3 = bitcast <8 x i16> %splat.splat to <2 x i64> [all …]
D	splat-const.ll	`19 %splat = shufflevector <4 x i32> %zero, <4 x i32> undef, <4 x i32> zeroinitializer 20 ret <4 x i32> %splat 38 %splat = shufflevector <4 x i32> %const, <4 x i32> undef, <4 x i32> zeroinitializer 39 ret <4 x i32> %splat`
D	shl-i64.ll	`16 %splat = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> zeroinitializer 17 %shl = shl <4 x i64> %0, %splat`
D	vector-shift-shl-512.ll	`95 %splat = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer 96 %shift = shl <8 x i64> %a, %splat 107 %splat = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer 108 %shift = shl <16 x i32> %a, %splat 121 %splat = shufflevector <32 x i16> %b, <32 x i16> undef, <32 x i32> zeroinitializer 122 %shift = shl <32 x i16> %a, %splat 152 %splat = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer 153 %shift = shl <64 x i8> %a, %splat`
D	vector-shift-lshr-512.ll	`98 %splat = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer 99 %shift = lshr <8 x i64> %a, %splat 110 %splat = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer 111 %shift = lshr <16 x i32> %a, %splat 124 %splat = shufflevector <32 x i16> %b, <32 x i16> undef, <32 x i32> zeroinitializer 125 %shift = lshr <32 x i16> %a, %splat 158 %splat = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer 159 %shift = lshr <64 x i8> %a, %splat`
D	splat-for-size.ll	`6 ; for size optimization using splat ops available with AVX and AVX2. 49 ; AVX can't do integer splats, so fake it: use vmovddup to splat 64-bit value. 62 ; and then we fake it: use vmovddup to splat 64-bit value. 82 ; AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value. 99 ; AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.`
/external/llvm/test/CodeGen/AMDGPU/
D	dagcombiner-bug-illegal-vec4-int-to-fp.ll	`19 %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer 20 store <4 x float> %splat, <4 x float> addrspace(1)* %out 33 %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer 34 store <4 x float> %splat, <4 x float> addrspace(1)* %out`
/external/llvm/test/CodeGen/ARM/
D	vdup.ll	336 ; Check that an SPR splat produces a vdup. 342 %splat.splatinsert = insertelement <2 x float> undef, float %conv, i32 0 343 …%splat.splat = shufflevector <2 x float> %splat.splatinsert, <2 x float> undef, <2 x i32> zeroinit… 344 %sub = fsub <2 x float> %splat.splat, %p 352 %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 0 353 …%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinit… 354 %sub = fsub <4 x float> %splat.splat, %p 362 %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 1 363 …%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> <i32 1, … 364 %sub = fsub <4 x float> %splat.splat, %p
/external/skia/src/opts/
D	Sk4px_SSE2.h	`63 __m128i splat = _mm_set_epi8(15,15,15,15, 11,11,11,11, 7,7,7,7, 3,3,3,3); in alphas() local 64 return Sk16b(_mm_shuffle_epi8(this->fVec, splat)); in alphas() 69 __m128i splat = _mm_set_epi8(3,3,3,3, 2,2,2,2, 1,1,1,1, 0,0,0,0); in Load4Alphas() local 70 return Sk16b(_mm_shuffle_epi8(_mm_cvtsi32_si128(as), splat)); in Load4Alphas()`
/external/llvm/test/CodeGen/PowerPC/
D	swaps-le-2.ll	`3 ; Test swap removal when a vector splat must be adjusted to make it legal. 66 ; Byte splat of element 5 (BE) becomes element 15-5 = 10 (LE) 69 ; Halfword splat of element 6 (BE) becomes element 7-6 = 1 (LE) 72 ; Word splat of element 1 (BE) becomes element 3-1 = 2 (LE)`
D	p8-scalar_vector_conversions.ll	6 ; to this, there will be a splat corresponding to the shufflevector. 16 %splat.splatinsert = insertelement <16 x i8> undef, i8 %0, i32 0 17 …%splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitial… 18 ret <16 x i8> %splat.splat 31 %splat.splatinsert = insertelement <8 x i16> undef, i16 %0, i32 0 32 …%splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitiali… 33 ret <8 x i16> %splat.splat 46 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 47 …%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitiali… 48 ret <4 x i32> %splat.splat [all …]
D	ctrloop-fp64.ll	`37 …%broadcast.splat.i = shufflevector <2 x i64> %broadcast.splatinsert.i, <2 x i64> undef, <2 x i32> … 44 store <2 x i64> %broadcast.splat.i, <2 x i64>* %1, align 8 48 store <2 x i64> %broadcast.splat.i, <2 x i64>* %3, align 8`
/external/antlr/antlr-3.4/runtime/Ruby/lib/antlr3/template/
D	parameter.rb	`9 elsif splat then "*#{ name }" 40 param.splat = options.fetch( :splat, false )`
/external/llvm/test/Analysis/CostModel/X86/
D	vshift-ashr-cost.ll	115 %splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer 116 %shift = ashr <2 x i64> %a, %splat 127 %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer 128 %shift = ashr <4 x i64> %a, %splat 140 %splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer 141 %shift = ashr <4 x i32> %a, %splat 153 %splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer 154 %shift = ashr <8 x i32> %a, %splat 165 %splat = shufflevector <8 x i16> %b, <8 x i16> undef, <8 x i32> zeroinitializer 166 %shift = ashr <8 x i16> %a, %splat [all …]
D	vshift-lshr-cost.ll	118 %splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer 119 %shift = lshr <2 x i64> %a, %splat 131 %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer 132 %shift = lshr <4 x i64> %a, %splat 144 %splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer 145 %shift = lshr <4 x i32> %a, %splat 157 %splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer 158 %shift = lshr <8 x i32> %a, %splat 169 %splat = shufflevector <8 x i16> %b, <8 x i16> undef, <8 x i32> zeroinitializer 170 %shift = lshr <8 x i16> %a, %splat [all …]
D	vshift-shl-cost.ll	119 %splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer 120 %shift = shl <2 x i64> %a, %splat 132 %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer 133 %shift = shl <4 x i64> %a, %splat 145 %splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer 146 %shift = shl <4 x i32> %a, %splat 158 %splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer 159 %shift = shl <8 x i32> %a, %splat 170 %splat = shufflevector <8 x i16> %b, <8 x i16> undef, <8 x i32> zeroinitializer 171 %shift = shl <8 x i16> %a, %splat [all …]
/external/llvm/test/Transforms/InstCombine/
D	vec_extract_elt.ll	`13 %splat = shufflevector <8 x i64> %vec, <8 x i64> undef, <8 x i32> zeroinitializer 14 %add = add <8 x i64> %splat, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>`
/external/llvm/test/Transforms/SLPVectorizer/X86/
D	commutativity.ll	`4 ; offers the possibility to splat/broadcast %c and thus make it profitable 16 ; Check that we correctly detect a splat/broadcast by leveraging the 19 ; CHECK-LABEL: @splat 21 define void @splat(i8 %a, i8 %b, i8 %c) {`

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