Searched refs:sqadd (Results 1 – 25 of 25) sorted by relevance
199 sqadd v18.4h,v6.4h,v7.4h200 sqadd v18.4h,v18.4h,v0.4h //vaddq_s32(i4_tmp1_t1, tmp_lvl_shift_t)202 sqadd v20.4h,v1.4h,v3.4h //vaddq_s32(i4_tmp2_t1, i4_tmp2_t2)203 sqadd v19.4h,v20.4h,v0.4h //vaddq_s32(i4_tmp2_t1, tmp_lvl_shift_t)208 sqadd v30.4h,v22.4h,v23.4h209 sqadd v30.4h,v30.4h,v0.4h //vaddq_s32(i4_tmp1_t1, tmp_lvl_shift_t) iii iteration212 sqadd v18.4h,v24.4h,v25.4h //vaddq_s32(i4_tmp2_t1, i4_tmp2_t2) iv iteration213 sqadd v31.4h,v18.4h,v0.4h254 sqadd v18.4h,v6.4h,v7.4h255 sqadd v18.4h,v18.4h,v0.4h //vaddq_s32(i4_tmp1_t1, tmp_lvl_shift_t)[all …]
215 sqadd v22.8h, v26.8h , v24.8h229 sqadd v22.8h, v26.8h , v24.8h297 sqadd v22.8h, v26.8h , v24.8h341 sqadd v22.8h, v26.8h , v24.8h
207 sqadd v0.8h, v0.8h , v30.8h208 sqadd v28.8h, v28.8h , v30.8h342 sqadd v0.8h, v26.8h , v30.8h
300 sqadd v22.8h, v26.8h , v24.8h344 sqadd v22.8h, v26.8h , v24.8h
9 sqadd v0.8b, v1.8b, v2.8b10 sqadd v0.16b, v1.16b, v2.16b11 sqadd v0.4h, v1.4h, v2.4h12 sqadd v0.8h, v1.8h, v2.8h13 sqadd v0.2s, v1.2s, v2.2s14 sqadd v0.4s, v1.4s, v2.4s15 sqadd v0.2d, v1.2d, v2.2d
6 sqadd b0, b1, b27 sqadd h10, h11, h128 sqadd s20, s21, s29 sqadd d17, d31, d8
839 sqadd v0.2s, v1.2s, v2.2d865 sqadd d0, s31, d2 define
346 sqadd.8b v0, v0, v0417 ; CHECK: sqadd.8b v0, v0, v0 ; encoding: [0x00,0x0c,0x20,0x0e]
5 ;CHECK: sqadd.8b8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)14 ;CHECK: sqadd.4h17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)23 ;CHECK: sqadd.2s26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)59 ;CHECK: sqadd.16b62 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)68 ;CHECK: sqadd.8h71 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)[all …]
12 declare <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16>, <4 x i16>)13 declare <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16>, <8 x i16>)14 declare <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32>, <2 x i32>)15 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)16 declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32)17 declare i16 @llvm.aarch64.neon.sqadd.i16(i16, i16)33 %retval = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc, <4 x i16> %prod)43 %retval = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %acc, <8 x i16> %prod)53 %retval = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %acc, <2 x i32> %prod)63 %retval = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %acc, <4 x i32> %prod)[all …]
5 ; CHECK: sqadd s0, s0, s18 %vqadd.i = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %vecext, i32 %vecext1) nounwind14 ; CHECK: sqadd d0, d0, d117 %vqadd.i = tail call i64 @llvm.aarch64.neon.sqadd.i64(i64 %vecext, i64 %vecext1) nounwind41 declare i64 @llvm.aarch64.neon.sqadd.i64(i64, i64) nounwind readnone42 declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32) nounwind readnone
33 …%sqadd = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> zeroinitializer, <4 x i32> %…34 %shuffle = shufflevector <4 x i32> %sqadd, <4 x i32> undef, <2 x i32> zeroinitializer99 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
274 …%vqdmlal17.i.i = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal15.…286 …%vqdmlal17.i.i = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal15.…300 …%vqdmlal11.i.i = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal9.i…312 …%vqdmlal11.i.i = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal9.i…573 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)574 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)
298 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)299 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)310 %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)321 %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)334 %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)347 %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)977 %tmp6 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)990 %tmp6 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)1004 %tmp6 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)1018 %tmp6 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)[all …]
33 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)35 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)1158 …%vqdmlal4.i = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal2…1169 …%vqdmlal4.i = tail call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal2…1181 …%vqdmlal4.i = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal2…1193 …%vqdmlal4.i = tail call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal2…2537 …%vqdmlal4.i = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal2…2548 …%vqdmlal4.i = tail call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal2…2560 …%vqdmlal4.i = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal2…2572 …%vqdmlal4.i = tail call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal2…
13 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)15 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)1694 …%vqdmlal4.i = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal2…1703 …%vqdmlal4.i = tail call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal2…1752 …%vqdmlal4.i.i = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmla…1763 …%vqdmlal4.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmla…
349 # CHECK: sqadd v0.16b, v1.16b, v2.16b352 # CHECK: sqadd v0.2s, v1.2s, v2.2s369 # CHECK: sqadd b20, b11, b15
329 # CHECK: sqadd.8b v0, v0, v0
27927 sqadd d1, d2, d4 0cd88fcd3077229ac0f64b3e6cef3344 895181f37bc6fd1ae21d96e27e2b3e38 5a9542d42227…27928 sqadd s1, s2, s4 056fd40c9dd98a51864916622a8ebf06 1ab47f49cb16141d9cd629bac3ba910b fb828a773e53…27929 sqadd h1, h2, h4 a4e2eef205b89a3a37b3337dd953a13c e62278444d339870161475c86ffe3fb1 ee27743c431a…27930 sqadd b1, b2, b4 ecc743f22e68768957468783bd137c9a f22fd257c56eb048d5e95effc7cbeddc 371a6497f3cd…27943 sqadd v1.2d, v2.2d, v4.2d 43662b17b4f2ddd6844e2d1be27cfd82 70d05ecb74a4c61bd65ad797754ddf61 f…27944 sqadd v1.4s, v2.4s, v4.4s 6dd9c611065ab94427a72da678b4e5d1 0baca4f1f2c8329a2516714cbba14fe6 c…27945 sqadd v1.2s, v2.2s, v4.2s 13969defc9ce4343cbc327a8b6df6932 3881cb7a98c69247cb83ea359ff8e05c a…27946 sqadd v1.8h, v2.8h, v4.8h 38331426c3a1a006f3b8fd12dfd32c59 fae238d92af20a584cb7264563263775 c…27947 sqadd v1.4h, v2.4h, v4.4h e1428f29b628f3c2249994d93664d2f9 56654f826c9ebfff2bc409704dfef6e6 0…27948 sqadd v1.16b, v2.16b, v4.16b 1259726c68b660abe279d0f2016500c7 4f9d74e92221d470edc077aba055c362 …[all …]
3712 DEFINE_TEST_NEON_3SAME(sqadd, Basic)3791 DEFINE_TEST_NEON_3SAME_SCALAR(sqadd, Basic)
2177 V(sqadd, Sqadd) \
2329 void sqadd(const VRegister& vd,
3249 V(sqadd, NEON_SQADD, true) \
3329 void sqadd(const VRegister& vd,
2916 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;3180 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;