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Searched refs:sqdmlal2 (Results 1 – 17 of 17) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-2velem.s116 sqdmlal2 v0.4s, v1.8h, v1.h[2]
117 sqdmlal2 v0.2d, v1.4s, v1.s[2]
118 sqdmlal2 v0.2d, v1.4s, v22.s[2]
Dneon-3vdiff.s251 sqdmlal2 v0.4s, v1.8h, v2.8h
252 sqdmlal2 v0.2d, v1.4s, v2.4s
Dneon-diagnostics.s2505 sqdmlal2 v0.4s, v1.8s, v2.8h
2506 sqdmlal2 v0.2d, v1.4d, v2.4s
2517 sqdmlal2 v0.8h, v1.16b, v2.16b
3291 sqdmlal2 v0.4h, v1.8h, v1.h[2]
3292 sqdmlal2 v0.4s, v1.8h, v1.h[8]
3293 sqdmlal2 v0.4s, v1.8h, v16.h[2]
3294 sqdmlal2 v0.2s, v1.4s, v1.s[2]
3295 sqdmlal2 v0.2d, v1.4s, v1.s[4]
3296 sqdmlal2 v0.2d, v1.4s, v22.s[4]
Darm64-advsimd.s1242 sqdmlal2.4s v0, v0, v0[1]
1244 sqdmlal2.2d v0, v0, v0[3]
1311 ; CHECK: sqdmlal2.4s v0, v0, v0[1] ; encoding: [0x00,0x30,0x50,0x4f]
1313 ; CHECK: sqdmlal2.2d v0, v0, v0[3] ; encoding: [0x00,0x38,0xa0,0x4f]
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-2velem-high.ll265 ; CHECK-NEXT: sqdmlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
281 ; CHECK-NEXT: sqdmlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h
293 ; CHECK-NEXT: sqdmlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
307 ; CHECK-NEXT: sqdmlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s
Darm64-vmul.ll327 ;CHECK: sqdmlal2.4s
340 ;CHECK: sqdmlal2.2d
997 ;CHECK: sqdmlal2.4s
1011 ;CHECK: sqdmlal2.2d
1797 ; CHECK: sqdmlal2.2d
1860 ; CHECK: sqdmlal2.2d
Darm64-neon-3vdiff.ll1747 ; CHECK: sqdmlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
1758 ; CHECK: sqdmlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
/external/vixl/src/vixl/a64/
Dsimulator-a64.h1579 LogicVRegister sqdmlal2(VectorFormat vform,
2183 V(sqdmlal2) \
Dmacro-assembler-a64.h2179 V(sqdmlal2, Sqdmlal2) \
2368 V(sqdmlal2, Sqdmlal2) \
Dassembler-a64.h2476 void sqdmlal2(const VRegister& vd,
3500 void sqdmlal2(const VRegister& vd,
Dlogic-a64.cc1047 LogicVRegister Simulator::sqdmlal2(VectorFormat vform, in sqdmlal2() function in vixl::Simulator
1055 return sqdmlal2(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmlal2()
3219 LogicVRegister Simulator::sqdmlal2(VectorFormat vform, in sqdmlal2() function in vixl::Simulator
Dsimulator-a64.cc2730 case NEON_SQDMLAL2: sqdmlal2(vf_l, rd, rn, rm); break; in VisitNEON3Different()
2867 Op = &Simulator::sqdmlal2; in VisitNEONByIndexedElement()
Dassembler-a64.cc2425 V(sqdmlal2, NEON_SQDMLAL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
3568 V(sqdmlal2, NEON_SQDMLAL_byelement, vn.IsVector() && vn.IsQ()) \ in NEON_FPBYELEMENT_LIST()
/external/vixl/doc/
Dsupported-instructions.md3357 void sqdmlal2(const VRegister& vd,
3366 void sqdmlal2(const VRegister& vd,
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt1727 # CHECK: sqdmlal2.4s v0, v0, v0[1]
1729 # CHECK: sqdmlal2.2d v0, v0, v0[3]
Dneon-instructions.txt1331 # CHECK: sqdmlal2 v0.4s, v1.8h, v2.8h
1332 # CHECK: sqdmlal2 v0.2d, v1.4s, v2.4s
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp27986 sqdmlal2 v29.2d, v20.4s, v3.s[1] 21b674ffc393b603dcc9f9ebc9340c5a 22b90b20674d3987599b3c96a4f5eb…
27987 sqdmlal2 v29.2d, v20.4s, v3.s[2] 064f4d843130aaba6bef434207a9ba61 0a567498fd881be2e56600326489d0…
27990 sqdmlal2 v29.4s, v20.8h, v3.h[1] a54665e8c25c61f114d008bfa012a42e afcfe17ee0c6d8042db32e3dcce017…
27991 sqdmlal2 v29.4s, v20.8h, v3.h[1] cac25d3cc6eefbff3e90f0049da310e6 21db87f16ed82d961887c9bf1a9c78…
28016 sqdmlal2 v2.2d, v11.4s, v29.4s 0c65e88fc2842a6c3ddec3ba0cd956ee 5740aec20abfb1cd9ccd20e0aa086cd7…
28018 sqdmlal2 v2.4s, v11.8h, v29.8h 20e8c5f6c741b4b259db11c251023f94 e1f95445bd188fb825739680240f17ee…