Searched refs:src0_abs (Results 1 – 10 of 10) sorted by relevance
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_structs.h | 1040 GLuint src0_abs:1; member
1059 GLuint src0_abs:1; member
1073 GLuint src0_abs:1; member
1089 GLuint src0_abs:1; member
1106 GLuint src0_abs:1; member
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| D | brw_disasm.c | 732 err |= control (file, "abs", _abs, inst->bits1.da3src.src0_abs, NULL); in src0_3src()
920 inst->bits2.da1.src0_abs, in src0()
931 inst->bits2.ia1.src0_abs, in src0()
948 inst->bits2.da16.src0_abs, in src0()
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| D | brw_optimize.c | 417 mov->bits2.da1.src0_abs != 0 || in brw_is_grf_to_mrf_mov()
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| D | brw_eu_emit.c | 248 insn->bits2.da1.src0_abs = reg.abs; in brw_set_src0()
795 insn->bits1.da3src.src0_abs = src0.abs; in brw_alu3()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 123 bits<1> src0_abs;
130 let Word1{0} = src0_abs;
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| D | R600Instructions.td | 97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
139 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
145 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
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| D | R600ExpandSpecialInstrs.cpp | 340 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_abs); in runOnMachineFunction()
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| D | R600InstrInfo.cpp | 1239 OPERAND_CASE(AMDGPU::OpName::src0_abs) in getSlotedOps()
1279 AMDGPU::OpName::src0_abs, in buildSlotOfVectorInstruction()
1376 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break; in getFlagOp()
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| D | EvergreenInstructions.td | 384 let src0_abs = 0;
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| D | R600ISelLowering.cpp | 2272 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs), in PostISelFolding()
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