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Searched refs:srl (Results 1 – 25 of 166) sorted by relevance

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/external/llvm/test/MC/Mips/
Drotations32.s24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
Drotations64.s24 # CHECK-64: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-64: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-64: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-64: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-64: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-64: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-64: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-64: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-64: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-64: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
Dmicromips-shift-instructions.s14 # CHECK-EL: srl $4, $3, 7 # encoding: [0x83,0x00,0x40,0x38]
25 # CHECK-EB: srl $4, $3, 7 # encoding: [0x00,0x83,0x38,0x40]
33 srl $4, $3, 7
/external/llvm/test/CodeGen/SystemZ/
Dshift-02.ll8 ; CHECK: srl %r2, 1
17 ; CHECK: srl %r2, 31
26 ; CHECK-NOT: srl %r2, 32
35 ; CHECK-NOT: srl %r2, -1{{.*}}
45 ; CHECK: srl %r2, 0(%r3)
54 ; CHECK: srl %r2, 10(%r3)
64 ; CHECK: srl %r2, 10(%r3)
76 ; CHECK: srl %r2, 4095(%r3)
87 ; CHECK: srl %r2, 0(%r3)
98 ; CHECK: srl %r2, 0({{%r[34]}})
[all …]
Dsetcc-02.ll11 ; CHECK-NEXT: srl %r2, 31
24 ; CHECK-NEXT: srl %r2, 31
36 ; CHECK-NEXT: srl %r2, 31
49 ; CHECK-NEXT: srl %r2, 31
85 ; CHECK-NEXT: srl %r2, 31
97 ; CHECK-NEXT: srl %r2, 31
133 ; CHECK-NEXT: srl %r2, 31
157 ; CHECK-NEXT: srl %r2, 31
169 ; CHECK-NEXT: srl %r2, 31
Dsetcc-01.ll11 ; CHECK-NEXT: srl %r2, 31
34 ; CHECK-NEXT: srl %r2, 31
69 ; CHECK-NEXT: srl %r2, 31
/external/llvm/test/CodeGen/Mips/
Dbswap.ll16 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
17 ; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
45 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $5, 8
46 ; MIPS16-DAG: srl $[[R1:[0-9]+]], $5, 24
56 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
57 ; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
/external/llvm/test/CodeGen/Mips/msa/
Dshift-dagcombine.ll31 ; CHECK-NOT: srl
33 ; CHECK-NOT: srl
39 ; CHECK-NOT: srl
42 ; CHECK-NOT: srl
/external/llvm/test/MC/Mips/mips1/
Dvalid.s102 … srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
103 … srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
104 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/llvm/test/CodeGen/AMDGPU/
Dno-shrink-extloads.ll104 %srl = lshr i64 %arg, 32
105 %trunc = trunc i64 %srl to i32
118 %srl = lshr i64 %load, 32
119 %trunc = trunc i64 %srl to i32
151 %srl = lshr i64 %arg, 32
152 %trunc = trunc i64 %srl to i8
165 %srl = lshr i64 %load, 32
166 %trunc = trunc i64 %srl to i8
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dbswap1.ll23 ; 32R1: srl $[[TMP2:[0-9]+]], $[[A_VAL]], 8
41 ; 32R1: srl $[[TMP1:[0-9]+]], $[[B_VAL]], 8
42 ; 32R1: srl $[[TMP2:[0-9]+]], $[[B_VAL]], 24
Dshift.ll4 ; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used.
24 ; CHECK: srl ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}
/external/valgrind/none/tests/mips64/
Dshift_instructions.stdout.exp-mips6417665 srl $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
17666 srl $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
17667 srl $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
17668 srl $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
17669 srl $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
17670 srl $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
17671 srl $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
17672 srl $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
17673 srl $t0, $t1, 0x00 :: rt 0x9823b6e, rs 0x9823b6e, imm 0x0000
17674 srl $t2, $t3, 0x1f :: rt 0x0, rs 0x9823b6e, imm 0x001f
[all …]
Dshift_instructions.stdout.exp-mips64r223553 srl $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
23554 srl $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
23555 srl $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
23556 srl $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
23557 srl $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000
23558 srl $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f
23559 srl $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f
23560 srl $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003
23561 srl $t0, $t1, 0x00 :: rt 0x9823b6e, rs 0x9823b6e, imm 0x0000
23562 srl $t2, $t3, 0x1f :: rt 0x0, rs 0x9823b6e, imm 0x001f
[all …]
/external/llvm/test/MC/Sparc/
Dsparc-alu-instructions.s55 ! CHECK: srl %g1, %g2, %g3 ! encoding: [0x87,0x30,0x40,0x02]
56 srl %g1, %g2, %g3
57 ! CHECK: srl %g1, 31, %g3 ! encoding: [0x87,0x30,0x60,0x1f]
58 srl %g1, 31, %g3
/external/llvm/test/CodeGen/BPF/
Dshifts.ll6 ; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
30 ; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
54 ; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
79 ; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
/external/llvm/test/MC/Mips/mips2/
Dvalid.s130 … srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
131 … srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
132 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/llvm/test/MC/Mips/mips32/
Dvalid.s160 … srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
161 … srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
162 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/llvm/test/CodeGen/SPARC/
Dctpop.ll18 ; V9: srl %o0, 0, %o0
23 ; SPARC64: srl %o0, 0, %o0
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td128 [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
131 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize16;
134 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize32;
137 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
142 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
145 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
149 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
153 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
158 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>;
161 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize16;
[all …]
/external/icu/icu4c/packaging/rpm/
Dicu.spec218 * Tue Aug 16 2003 Steven Loomis <srl@jtcsv.com>
220 * Thu Jun 05 2003 Steven Loomis <srl@jtcsv.com>
222 * Fri Dec 27 2002 Steven Loomis <srl@jtcsv.com>
224 * Fri Sep 27 2002 Steven Loomis <srl@jtcsv.com>
/external/llvm/test/MC/Mips/mips3/
Dvalid.s195 … srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
196 … srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
197 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/llvm/test/MC/Mips/mips32r3/
Dvalid.s195 … srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
196 … srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
197 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s195 … srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
196 … srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
197 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
/external/llvm/test/MC/Mips/mips32r5/
Dvalid.s196 … srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
197 … srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
198 … srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]

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