| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-shift.s | 123 srsra v0.8b, v1.8b, #3
124 srsra v0.4h, v1.4h, #3
125 srsra v0.2s, v1.2s, #3
126 srsra v0.16b, v1.16b, #3
127 srsra v0.8h, v1.8h, #3
128 srsra v0.4s, v1.4s, #3
129 srsra v0.2d, v1.2d, #3
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| D | neon-scalar-shift-imm.s | 50 srsra d15, d11, #19
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| D | arm64-advsimd.s | 1376 srsra d0, d0, #1 define
1425 ; CHECK: srsra d0, d0, #1 ; encoding: [0x00,0x34,0x7f,0x5f]
1538 srsra.8b v0, v0, #1
1539 srsra.16b v0, v0, #2
1540 srsra.4h v0, v0, #3
1541 srsra.8h v0, v0, #4
1542 srsra.2s v0, v0, #5
1543 srsra.4s v0, v0, #6
1544 srsra.2d v0, v0, #7
1710 ; CHECK: srsra.8b v0, v0, #1 ; encoding: [0x00,0x34,0x0f,0x0f]
[all …]
|
| D | neon-diagnostics.s | 1576 srsra v0.8b, v1.8h, #3
1577 srsra v0.4h, v1.4s, #3
1578 srsra v0.2s, v1.2d, #3
1579 srsra v0.16b, v1.16b, #9
1580 srsra v0.8h, v1.8h, #17
1581 srsra v0.4s, v1.4s, #33
1582 srsra v0.2d, v1.2d, #65
4973 srsra d15, d11, #99
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 1831 # CHECK: srsra d0, d0, #63
2113 # CHECK: srsra.8b v0, v0, #7
2114 # CHECK: srsra.16b v0, v0, #6
2115 # CHECK: srsra.4h v0, v0, #13
2116 # CHECK: srsra.8h v0, v0, #12
2117 # CHECK: srsra.2s v0, v0, #27
2118 # CHECK: srsra.4s v0, v0, #26
2119 # CHECK: srsra.2d v0, v0, #57
|
| D | neon-instructions.txt | 828 # CHECK: srsra v0.8b, v1.8b, #3
829 # CHECK: srsra v0.4h, v1.4h, #3
830 # CHECK: srsra v0.2s, v1.2s, #3
831 # CHECK: srsra v0.16b, v1.16b, #3
832 # CHECK: srsra v0.8h, v1.8h, #3
833 # CHECK: srsra v0.4s, v1.4s, #3
834 # CHECK: srsra v0.2d, v1.2d, #3
1852 # CHECK: srsra d15, d11, #19
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vshift.ll | 1445 ;CHECK: srsra.8b v0, {{v[0-9]+}}, #1
1455 ;CHECK: srsra.4h v0, {{v[0-9]+}}, #1
1465 ;CHECK: srsra.2s v0, {{v[0-9]+}}, #1
1475 ;CHECK: srsra.16b v0, {{v[0-9]+}}, #1
1485 ;CHECK: srsra.8h v0, {{v[0-9]+}}, #1
1495 ;CHECK: srsra.4s v0, {{v[0-9]+}}, #1
1505 ;CHECK: srsra.2d v0, {{v[0-9]+}}, #1
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 28620 srsra d5, d28, #1 fb6bd604b83bfb851cbe1c439ce285fa 5a0ae8799eadc8c9023619cf0ccbf4ab 00000000000…
28621 srsra d5, d28, #32 976c2f95dcef65994633a260d37e67e0 87bb84d0cd04724641473c0f0fa44d22 0000000000…
28622 srsra d5, d28, #64 b8a21383887898dce1c81be83cfc856c dc43edce054d982fad02df6e4b9d217a 0000000000…
28626 srsra v6.2d, v27.2d, #1 c3fd232d57b4def4a9ebe37803fee3b2 cfccce146bed89962749ac95ddf534f1 abe3…
28627 srsra v6.2d, v27.2d, #32 56ce892d9eb8413d71e361c0134d8303 245f3c4d877f23f1aed4a740ee942fed 56c…
28628 srsra v6.2d, v27.2d, #64 d49c53e7dbaa8361999b97e64c101614 fce8e678b078f3df2d183200401e7560 d49…
28629 srsra v6.4s, v27.4s, #1 9e48e13a6e6c034280f5e5ca0f25fac4 b8452d7547b85a4103f4aeb73473662c 7a6b…
28630 srsra v6.4s, v27.4s, #16 13b09407b5dc21be87cfac4cba6d92f5 b7587024ab1fb6f7914a7a432973602f 13b…
28631 srsra v6.4s, v27.4s, #32 94b5cb2f13db3db60d0a4c4bb0c83b85 59ff0f653c8d6ae135f8f78580fec64a 94b…
28632 srsra v6.2s, v27.2s, #1 ff1b6b175be2d3df52df845d98f4f55d 3c9c985cf83f673c77f273019b6e1e7b 0000…
[all …]
|
| /external/vixl/test/ |
| D | test-simulator-a64.cc | 3874 DEFINE_TEST_NEON_2OPIMM(srsra, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
3907 DEFINE_TEST_NEON_2OPIMM_SCALAR_D(srsra, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
|
| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.cc | 3674 case NEON_SRSRA_scalar: srsra(vf, rd, rn, right_shift); break; in VisitNEONScalarShiftImmediate()
3736 case NEON_SRSRA: srsra(vf, rd, rn, right_shift); break; in VisitNEONShiftImmediate()
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| D | simulator-a64.h | 2016 LogicVRegister srsra(VectorFormat vform,
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| D | macro-assembler-a64.h | 2418 V(srsra, Srsra) \
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| D | assembler-a64.h | 3287 void srsra(const VRegister& vd,
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| D | logic-a64.cc | 1798 LogicVRegister Simulator::srsra(VectorFormat vform, in srsra() function in vixl::Simulator
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| D | assembler-a64.cc | 4371 void Assembler::srsra(const VRegister& vd, in srsra() function in vixl::Assembler
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| /external/vixl/doc/ |
| D | supported-instructions.md | 3683 void srsra(const VRegister& vd,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4631 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4683 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
|