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/external/libhevc/common/arm64/
Dihevc_intra_pred_luma_vert.s233 sshr d24, d24,#8
236 sshr d25, d25,#8
243 sshr d24, d24,#8
246 sshr d25, d25,#8
268 sshr d24, d24,#8
271 sshr d25, d25,#8
281 sshr d24, d24,#8
284 sshr d25, d25,#8
298 sshr d24, d24,#8
301 sshr d25, d25,#8
[all …]
Dihevc_intra_pred_luma_dc.s138 sshr d7, d7,#32 define
257 sshr d3, d3,#8 //row 0 shift (prol) (first value to be ignored) define
266 sshr d3, d3,#8 //row 1 shift (prol) define
275 sshr d3, d3,#8 //row 2 shift (prol) define
283 sshr d3, d3,#8 //row 3 shift (prol) define
291 sshr d3, d3,#8 //row 4 shift (prol) define
299 sshr d3, d3,#8 //row 5 shift (prol) define
310 sshr d3, d3,#8 //row 6 shift (prol) define
317 sshr d3, d3,#8 //row 7 shift (prol) define
346 sshr d3, d3,#8 //row 9 shift (prol) define
[all …]
Dihevc_intra_pred_luma_horz.s212 sshr v24.8h, v24.8h,#1
226 sshr v24.8h, v24.8h,#1
294 sshr v24.8h, v24.8h,#1
338 sshr v24.8h, v24.8h,#1
Dihevc_intra_pred_chroma_horz.s297 sshr v24.8h, v24.8h,#1
341 sshr v24.8h, v24.8h,#1
Dihevc_intra_pred_luma_mode_3_to_9.s164 sshr v22.8h, v22.8h,#5
296 sshr v12.8h, v12.8h,#5
408 sshr v14.8h, v14.8h,#5
503 sshr v22.8h, v22.8h,#5
Dihevc_intra_pred_filters_luma_mode_11_to_17.s284 sshr v22.8h, v22.8h,#5
416 sshr v12.8h, v12.8h,#5
529 sshr v14.8h, v14.8h,#5
632 sshr v22.8h, v22.8h,#5
Dihevc_intra_pred_chroma_mode_3_to_9.s157 sshr v22.8h, v22.8h,#5
297 sshr v25.8h, v25.8h,#5
419 sshr v14.8h, v14.8h,#5
Dihevc_intra_pred_filters_chroma_mode_11_to_17.s276 sshr v22.8h, v22.8h,#5
419 sshr v12.8h, v12.8h,#5
548 sshr v14.8h, v14.8h,#5
Dihevc_deblk_luma_vert.s531 sshr v16.8h,v16.8h,#1
589 sshr v2.8h,v2.8h,#1
Dihevc_deblk_luma_horz.s518 sshr v0.8b,v0.8b,#1
/external/libavc/common/armv8/
Dih264_iquant_itrans_recon_av8.s169 sshr v8.4h, v1.4h, #1 // d1>>1
170 sshr v9.4h, v3.4h, #1 // d3>>1
200 sshr v18.4h, v11.4h, #1 // q0>>1
201 sshr v19.4h, v13.4h, #1 // q1>>1
357 sshr v8.4h, v1.4h, #1 // d1>>1
358 sshr v9.4h, v3.4h, #1 // d3>>1
389 sshr v18.4h, v11.4h, #1 // q0>>1
390 sshr v19.4h, v13.4h, #1 // q1>>1
641 sshr v16.8h, v9.8h, #1 //(pi2_tmp_ptr[1] >> 1)
642 sshr v17.8h, v10.8h, #1 //(pi2_tmp_ptr[2] >> 1)
[all …]
/external/llvm/test/MC/AArch64/
Dneon-simd-shift.s8 sshr v0.8b, v1.8b, #3
9 sshr v0.4h, v1.4h, #3
10 sshr v0.2s, v1.2s, #3
11 sshr v0.16b, v1.16b, #3
12 sshr v0.8h, v1.8h, #3
13 sshr v0.4s, v1.4s, #3
14 sshr v0.2d, v1.2d, #3
Dneon-scalar-shift-imm.s8 sshr d15, d16, #12
Darm64-advsimd.s1377 sshr d0, d0, #1 define
1426 ; CHECK: sshr d0, d0, #1 ; encoding: [0x00,0x04,0x7f,0x5f]
1551 sshr.8b v0, v0, #1
1552 sshr.16b v0, v0, #2
1553 sshr.4h v0, v0, #3
1554 sshr.8h v0, v0, #4
1555 sshr.2s v0, v0, #5
1556 sshr.4s v0, v0, #6
1557 sshr.2d v0, v0, #7
1558 sshr.8b v0, v0, #1
[all …]
Dneon-diagnostics.s1378 sshr v0.8b, v1.8h, #3
1379 sshr v0.4h, v1.4s, #3
1380 sshr v0.2s, v1.2d, #3
1381 sshr v0.16b, v1.16b, #9
1382 sshr v0.8h, v1.8h, #17
1383 sshr v0.4s, v1.4s, #33
1384 sshr v0.2d, v1.2d, #65
4907 sshr d15, d16, #99
4913 sshr d15, s16, #31
/external/llvm/test/CodeGen/AArch64/
Dcomplex-int-to-fp.ll34 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
55 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
93 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
112 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
149 ; CHECK: sshr.4h [[VAL16:v[0-9]+]], [[TMP]], #8
Darm64-vselect.ll9 ; sshr.4s v0, v0, #31
Darm64-neon-simd-shift.ll5 ; CHECK: sshr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #3
12 ; CHECK: sshr {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #3
19 ; CHECK: sshr {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #3
26 ; CHECK: sshr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #3
33 ; CHECK: sshr {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #3
40 ; CHECK: sshr {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #3
47 ; CHECK: sshr {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #3
Darm64-vshr.ll51 ; CHECK: sshr d0, d0, #63
/external/valgrind/none/tests/arm64/
Dfp_and_simd.c4124 GEN_SHIFT_TEST(sshr, 2d, 2d, 1)
4125 GEN_SHIFT_TEST(sshr, 2d, 2d, 13)
4126 GEN_SHIFT_TEST(sshr, 2d, 2d, 64)
4127 GEN_SHIFT_TEST(sshr, 4s, 4s, 1)
4128 GEN_SHIFT_TEST(sshr, 4s, 4s, 13)
4129 GEN_SHIFT_TEST(sshr, 4s, 4s, 32)
4130 GEN_SHIFT_TEST(sshr, 2s, 2s, 1)
4131 GEN_SHIFT_TEST(sshr, 2s, 2s, 13)
4132 GEN_SHIFT_TEST(sshr, 2s, 2s, 32)
4133 GEN_SHIFT_TEST(sshr, 8h, 8h, 1)
[all …]
Dfp_and_simd.stdout.exp28442 sshr d5, d28, #1 30e7ff33ec012bda586f71352f0b881f 712c2158a8a20c0e84c1f3c12c7eb494 000000000000…
28443 sshr d5, d28, #32 8a7039329795b2ff67396a5f315682ff ef2175aa69cfbcbf73893b2831e3bc59 00000000000…
28444 sshr d5, d28, #64 589e1f533e40dfe95d6b64cf633d3788 79b34d563f8b69ece2b15b0c7f5bd77e 00000000000…
28467 sshr v8.2d, v7.2d, #1 aa076b9eb96f3d31329ee02fdea9d4db d503b5cf5cb79e98194f7017ef54ea6d fpsr=0000…
28468 sshr v8.2d, v7.2d, #13 29f31d1948e8be87dbbbc2d0680edf1f 00014f98e8ca4745fffeddde16834076 fpsr=000…
28469 sshr v8.2d, v7.2d, #64 deca058ed08ad3a01874ae74793c039e ffffffffffffffff0000000000000000 fpsr=000…
28470 sshr v8.4s, v7.4s, #1 17888d9add8f2758b44591381cee6bb6 0bc446cdeec793acda22c89c0e7735db fpsr=0000…
28471 sshr v8.4s, v7.4s, #13 ab83794ff289086b358f995941224b64 fffd5c1bffff94480001ac7c00020912 fpsr=000…
28472 sshr v8.4s, v7.4s, #32 5712cc9e312eac535e5b8be6a6f7ffca 000000000000000000000000ffffffff fpsr=000…
28473 sshr v8.2s, v7.2s, #1 d0ba7be59f49a91cf031edb40823d2ca 0000000000000000f818f6da0411e965 fpsr=0000…
[all …]
/external/vixl/src/vixl/a64/
Dlogic-a64.cc1767 LogicVRegister Simulator::sshr(VectorFormat vform, in sshr() function in vixl::Simulator
1783 LogicVRegister shifted_reg = sshr(vform, temp, src, shift); in ssra()
1803 LogicVRegister shifted_reg = sshr(vform, temp, src, shift).Round(vform); in srsra()
2696 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift); in sqshrn()
2708 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift); in sqshrn2()
2720 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc); in sqrshrn()
2732 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc); in sqrshrn2()
2744 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift); in sqshrun()
2756 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift); in sqshrun2()
2768 LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc); in sqrshrun()
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt1832 # CHECK: sshr d0, d0, #63
2126 # CHECK: sshr.8b v0, v0, #7
2127 # CHECK: sshr.16b v0, v0, #6
2128 # CHECK: sshr.4h v0, v0, #13
2129 # CHECK: sshr.8h v0, v0, #12
2130 # CHECK: sshr.2s v0, v0, #27
2131 # CHECK: sshr.4s v0, v0, #26
2132 # CHECK: sshr.2d v0, v0, #57
2133 # CHECK: sshr.8b v0, v0, #7
Dneon-instructions.txt720 # CHECK: sshr v0.8b, v1.8b, #3
721 # CHECK: sshr v0.4h, v1.4h, #3
722 # CHECK: sshr v0.2s, v1.2s, #3
723 # CHECK: sshr v0.16b, v1.16b, #3
724 # CHECK: sshr v0.8h, v1.8h, #3
725 # CHECK: sshr v0.4s, v1.4s, #3
726 # CHECK: sshr v0.2d, v1.2d, #3
1816 # CHECK: sshr d15, d16, #12
/external/boringssl/linux-aarch64/crypto/modes/
Dghashv8-armx64.S20 sshr v17.4s,v17.4s,#31 //broadcast carry bit

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