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Searched refs:ssubl2 (Results 1 – 15 of 15) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-3vdiff.s57 ssubl2 v0.8h, v1.16b, v2.16b
58 ssubl2 v0.4s, v1.8h, v2.8h
59 ssubl2 v0.2d, v1.4s, v2.4s
Dneon-diagnostics.s2169 ssubl2 v0.8h, v1.16h, v2.16b
2170 ssubl2 v0.4s, v1.8s, v2.8h
2171 ssubl2 v0.2d, v1.4d, v2.4s
/external/llvm/test/CodeGen/AArch64/
Darm64-vsub.ll160 ;CHECK: ssubl2.8h
175 ;CHECK: ssubl2.4s
190 ;CHECK: ssubl2.2d
Darm64-neon-3vdiff.ll361 ; CHECK: ssubl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
373 ; CHECK: ssubl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
385 ; CHECK: ssubl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
Darm64-vadd.ll792 ; CHECK: ssubl2.2d
/external/libavc/common/armv8/
Dih264_iquant_itrans_recon_av8.s656 ssubl2 v23.4s, v13.8h, v11.8h
662 ssubl2 v27.4s, v15.8h, v9.8h
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1160 # CHECK: ssubl2 v0.8h, v1.16b, v2.16b
1161 # CHECK: ssubl2 v0.4s, v1.8h, v2.8h
1162 # CHECK: ssubl2 v0.2d, v1.4s, v2.4s
/external/vixl/src/vixl/a64/
Dsimulator-a64.h1884 LogicVRegister ssubl2(VectorFormat vform,
Dmacro-assembler-a64.h2193 V(ssubl2, Ssubl2) \
Dassembler-a64.h3184 void ssubl2(const VRegister& vd,
Dsimulator-a64.cc2708 case NEON_SSUBL2: ssubl2(vf_l, rd, rn, rm); break; in VisitNEON3Different()
Dlogic-a64.cc2935 LogicVRegister Simulator::ssubl2(VectorFormat vform, in ssubl2() function in vixl::Simulator
Dassembler-a64.cc2419 V(ssubl2, NEON_SSUBL2, vn.IsVector() && vn.IsQ()) \
/external/vixl/doc/
Dsupported-instructions.md3746 void ssubl2(const VRegister& vd,
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp27388 ssubl2 v2.2d, v11.4s, v29.4s fdcf7899f3535ec8e568421b4b5a87ff 2254cb3c0d5ebce294f50badc21c63ee …
27390 ssubl2 v2.4s, v11.8h, v29.8h a8c5ad99e90689d8abbddc00561cc574 9a39605088e553101fab6422d8f57c4c …
27392 ssubl2 v2.8h, v11.16b, v29.16b 7179d5a53bc994311da1901bfbd0f2a1 17417ab62d89ab16c3724f43eca5767f…