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Searched refs:sth (Results 1 – 25 of 66) sorted by relevance

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/external/webrtc/webrtc/modules/audio_coding/codecs/isac/main/source/
Dlattice.c38 float sth[MAX_AR_MODEL_ORDER]; in WebRtcIsac_NormLatticeFilterMa() local
53 WebRtcIsac_Dir2Lat(a,orderCoef,sth,cth); in WebRtcIsac_NormLatticeFilterMa()
76 f[i][0] = inv_cth[i-1]*(f[i-1][0] + sth[i-1]*stateG[i-1]); in WebRtcIsac_NormLatticeFilterMa()
77 g[i][0] = cth[i-1]*stateG[i-1] + sth[i-1]* f[i][0]; in WebRtcIsac_NormLatticeFilterMa()
85 f[k+1][n+1] = inv_cth[k]*(f[k][n+1] + sth[k]*g[k][n]); in WebRtcIsac_NormLatticeFilterMa()
86 g[k+1][n+1] = cth[k]*g[k][n] + sth[k]* f[k+1][n+1]; in WebRtcIsac_NormLatticeFilterMa()
119 float sth[MAX_AR_MODEL_ORDER]; in WebRtcIsac_NormLatticeFilterAr() local
133 WebRtcIsac_Dir2Lat(a,orderCoef,sth,cth); in WebRtcIsac_NormLatticeFilterAr()
151 ARf[i][0] = cth[i]*ARf[i+1][0] - sth[i]*stateG[i]; in WebRtcIsac_NormLatticeFilterAr()
152 ARg[i+1][0] = sth[i]*ARf[i+1][0] + cth[i]* stateG[i]; in WebRtcIsac_NormLatticeFilterAr()
[all …]
Dcodec.h229 void WebRtcIsac_Dir2Lat(double* a, int orderCoef, float* sth, float* cth);
/external/llvm/test/CodeGen/BPF/
Dundef.ll45 ; CHECK: sth 6(r1), r2
46 ; CHECK: sth 4(r1), r2
47 ; CHECK: sth 2(r1), r2
48 ; CHECK: sth 24(r10), r2
49 ; CHECK: sth 22(r10), r2
50 ; CHECK: sth 20(r10), r2
51 ; CHECK: sth 18(r10), r2
52 ; CHECK: sth 16(r10), r2
53 ; CHECK: sth 14(r10), r2
54 ; CHECK: sth 12(r10), r2
[all …]
Dcc_args_be.ll46 ; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
53 ; CHECK: sth 2(r2), r1 # encoding: [0x6b,0x21,0x00,0x02,0x00,0x00,0x00,0x00]
54 ; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
78 ; CHECK: sth 0(r4), r1
82 ; CHECK: sth 0(r4), r3
89 ; CHECK: sth 0(r4), r1
93 ; CHECK: sth 0(r4), r3
Dcc_args.ll45 ; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
52 ; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
53 ; CHECK: sth 2(r2), r1 # encoding: [0x6b,0x12,0x02,0x00,0x00,0x00,0x00,0x00]
77 ; CHECK: sth 0(r4), r1
81 ; CHECK: sth 0(r4), r3
88 ; CHECK: sth 0(r4), r1
92 ; CHECK: sth 0(r4), r3
Dcc_ret.ll8 ; CHECK: sth 0(r1), r0
/external/llvm/test/CodeGen/SystemZ/
Dcond-store-02.ll14 ; CHECK: sth %r3, 0(%r2)
30 ; CHECK: sth %r3, 0(%r2)
47 ; CHECK: sth %r3, 0(%r2)
65 ; CHECK: sth %r3, 0(%r2)
84 ; CHECK: sth %r3, 0(%r2)
102 ; CHECK: sth %r3, 0(%r2)
121 ; CHECK: sth %r3, 0(%r2)
139 ; CHECK: sth %r3, 0(%r2)
158 ; CHECK: sth %r3, 0(%r2)
176 ; CHECK: sth %r3, 0(%r2)
[all …]
Dint-move-05.ll8 ; CHECK: sth %r3, 0(%r2)
17 ; CHECK: sth %r3, 0(%r2)
27 ; CHECK: sth %r3, 0(%r2)
37 ; CHECK: sth %r3, 4094(%r2)
69 ; CHECK: sth %r3, 0(%r2)
101 ; CHECK: sth %r3, 0(%r2)
111 ; CHECK: sth %r4, 4094({{%r3,%r2|%r2,%r3}})
Datomic-store-02.ll7 ; CHECK: sth %r2, 0(%r3)
Dunaligned-01.ll29 ; CHECK: sth %r2, 0(%r3)
Dfp-move-10.ll52 ; CHECK: sth [[REG]], 0(%r2)
/external/llvm/test/MC/Sparc/
Dsparc-mem-instructions.s67 ! CHECK: sth %o2, [%i0+%l6] ! encoding: [0xd4,0x36,0x00,0x16]
68 sth %o2, [%i0 + %l6]
69 ! CHECK: sth %o2, [%i0+32] ! encoding: [0xd4,0x36,0x20,0x20]
70 sth %o2, [%i0 + 32]
71 ! CHECK: sth %o2, [%g1] ! encoding: [0xd4,0x30,0x40,0x00]
72 sth %o2, [%g1]
/external/llvm/test/CodeGen/PowerPC/
Djaggedstructs.ll28 ; CHECK: sth {{[0-9]+}}, 53(1)
35 ; CHECK: sth {{[0-9]+}}, 70(1)
41 ; CHECK: sth {{[0-9]+}}, 77(1)
Dpeephole-align.ll84 ; POWER7-DAG: sth [[REG0_1]], h2v@toc@l([[REGSTRUCT]])
85 ; POWER7-DAG: sth [[REG1_1]], h2v@toc@l+2([[REGSTRUCT]])
93 ; POWER8-DAG: sth [[REG0_1]], 0([[REGSTRUCT]])
94 ; POWER8-DAG: sth [[REG1_1]], 2([[REGSTRUCT]])
112 ; CHECK-DAG: sth [[REG0_1]], h2v@toc@l([[REGSTRUCT]])
113 ; CHECK-DAG: sth [[REG1_1]], h2v@toc@l+2([[REGSTRUCT]])
217 ; POWER7-DAG: sth [[REG0_1]], h4v@toc@l([[REGSTRUCT]])
218 ; POWER7-DAG: sth [[REG1_1]], h4v@toc@l+2([[REGSTRUCT]])
219 ; POWER7-DAG: sth [[REG2_1]], h4v@toc@l+4([[REGSTRUCT]])
220 ; POWER7-DAG: sth [[REG3_1]], h4v@toc@l+6([[REGSTRUCT]])
[all …]
Dstructsinregs.ll105 ; CHECK: sth 4, 62(1)
143 ; CHECK: sth {{[0-9]+}}, 69(1)
146 ; CHECK: sth {{[0-9]+}}, 94(1)
149 ; CHECK: sth {{[0-9]+}}, 101(1)
192 ; CHECK: sth 4, 62(1)
Dvec_insert.ll1 ; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep sth
Dunaligned.ll14 ; CHECK: sth
18 ; CHECK-VSX: sth
Dstructsinmem.ll63 ; CHECK: sth {{[0-9]+}}, 126(1)
152 ; CHECK: sth {{[0-9]+}}, 126(1)
154 ; CHECK: sth {{[0-9]+}}, 133(1)
158 ; CHECK: sth {{[0-9]+}}, 158(1)
161 ; CHECK: sth {{[0-9]+}}, 165(1)
Dpr13891.ll9 ; CHECK: sth 3, {{[0-9]+}}(1)
Dvec_extload.ll33 ; Same as v16si8_sext_in_reg, expands to load/store halfwords (lhz/sth).
/external/llvm/test/MC/Disassembler/Sparc/
Dsparc-mem.txt135 # CHECK: sth %o2, [%i0+%l6]
138 # CHECK: sth %o2, [%i0+32]
141 # CHECK: sth %o2, [%g1]
144 # CHECK: sth %o2, [%g1]
/external/llvm/test/CodeGen/Generic/
Dannotate.ll5 @.str = private unnamed_addr constant [4 x i8] c"sth\00", section "llvm.metadata"
Dptr-annotate.ll7 @.str = private unnamed_addr constant [4 x i8] c"sth\00", section "llvm.metadata"
/external/llvm/test/CodeGen/Hexagon/
Dcirc_st.ll62 %1 = tail call i8* @llvm.hexagon.circ.sth(i8* %0, i32 0, i32 %or, i32 -2)
68 declare i8* @llvm.hexagon.circ.sth(i8*, i32, i32, i32) nounwind
Dbrev_st.ll66 %1 = tail call i8* @llvm.hexagon.brev.sth(i8* %0, i32 0, i32 %shl)
72 declare i8* @llvm.hexagon.brev.sth(i8*, i32, i32) nounwind

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