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Searched refs:subhn (Results 1 – 14 of 14) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Darm64-vsub.ll5 ;CHECK: subhn.8b
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
14 ;CHECK: subhn.4h
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.subhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
23 ;CHECK: subhn.2s
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.subhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
32 ;CHECK: subhn.8b
34 %vsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
35 …%vsubhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nou…
42 ;CHECK: subhn.4h
[all …]
Darm64-vadd.ll876 ;CHECK: subhn.8b
887 ;CHECK: subhn.4h
898 ;CHECK: subhn.2s
Darm64-neon-3vdiff.ll811 ; CHECK: subhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
821 ; CHECK: subhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
831 ; CHECK: subhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
841 ; CHECK: subhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
851 ; CHECK: subhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
861 ; CHECK: subhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
/external/valgrind/none/tests/arm64/
Dfp_and_simd.c2722 GEN_BINARY_TEST(subhn, 2s, 2d, 2d)
2724 GEN_BINARY_TEST(subhn, 4h, 4s, 4s)
2726 GEN_BINARY_TEST(subhn, 8b, 8h, 8h)
Dfp_and_simd.stdout.exp26953 subhn v9.2s, v7.2d, v8.2d 770ae1e5aeefe6d6c7f9e416321beb52 86ea94dee9e1b968dcb4639e9c502b51 0000…
26955 subhn v9.4h, v7.4s, v8.4s fe44f317ecb1f9c87aa050364ebba8c8 0c2ed4b510f0915327404e40867e04c7 0000…
26957 subhn v9.8b, v7.8h, v8.8h 104f1ec3caa4b8807ad2d4a080b53fc6 b17155040e7edc2397c3b66bfa95bd22 0000…
/external/vixl/src/vixl/a64/
Dsimulator-a64.h2156 V(subhn) \
Dmacro-assembler-a64.h2197 V(subhn, Subhn) \
Dassembler-a64.h3577 void subhn(const VRegister& vd,
Dsimulator-a64.cc2747 case NEON_SUBHN: subhn(vf, rd, rn, rm); break; in VisitNEON3Different()
Dlogic-a64.cc3351 LogicVRegister Simulator::subhn(VectorFormat vform, in subhn() function in vixl::Simulator
Dassembler-a64.cc2447 V(subhn, NEON_SUBHN, vd.IsD()) \
/external/vixl/test/
Dtest-simulator-a64.cc3831 DEFINE_TEST_NEON_3DIFF_NARROW(subhn, Basic)
/external/vixl/doc/
Dsupported-instructions.md3892 void subhn(const VRegister& vd,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td3425 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3515 // CodeGen patterns for addhn and subhn instructions, which can actually be