| /external/llvm/test/CodeGen/ARM/ |
| D | fast-isel-icmp.ll | 38 ; ARM: sxtb r0, r0
39 ; ARM: sxtb r1, r1
42 ; THUMB: sxtb r0, r0
43 ; THUMB: sxtb r1, r1
|
| D | sxt_rot.ll | 5 ; CHECK: sxtb r0, r0
13 ; CHECK: sxtb r0, r0
|
| D | fast-isel-fold.ll | 78 ; ARM-NOT: sxtb
81 ; THUMB-NOT: sxtb
|
| D | fast-isel-conversion.ll | 40 ; ARM: sxtb r0, r0
44 ; THUMB: sxtb r0, r0
86 ; ARM: sxtb r0, r0
90 ; THUMB: sxtb r0, r0
|
| D | fast-isel-ext.ll | 85 ; v7: sxtb r0, r0
92 ; v7: sxtb r0, r0
|
| D | fast-isel-deadcode.ll | 15 ; THUMB-NOT: sxtb
|
| D | fast-isel.ll | 104 ; THUMB: sxtb
108 ; ARM: sxtb
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 174 add w1, w2, w3, sxtb
183 ; CHECK: add w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x0b]
191 add x1, x2, w3, sxtb
198 ; CHECK: add x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x8b]
218 sub w1, w2, w3, sxtb
227 ; CHECK: sub w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x4b]
235 sub x1, x2, w3, sxtb
242 ; CHECK: sub x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xcb]
262 adds w1, w2, w3, sxtb
271 ; CHECK: adds w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x2b]
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | addsub_ext.ll | 45 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb
50 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb #1
56 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb
61 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb #4
73 ; CHECK: cmp {{x[0-9]+}}, {{w[0-9]+}}, sxtb
120 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb
125 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb #1
131 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb
136 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb #4
|
| D | arm64-fast-isel-icmp.ll | 166 ; CHECK: sxtb w0, w0
167 ; CHECK-NEXT: cmp w0, w1, sxtb
187 ; CHECK: sxtb w0, w0
188 ; CHECK-NEXT: cmp w0, w1, sxtb
222 ; CHECK: sxtb w0, w0
|
| D | fast-isel-int-ext2.ll | 81 ; CHECK-NOT: sxtb
109 ; CHECK-NOT: sxtb
222 ; CHECK-NOT: sxtb
250 ; CHECK-NOT: sxtb
368 ; CHECK-NOT: sxtb
398 ; CHECK-NOT: sxtb
|
| D | fast-isel-int-ext.ll | 208 ; CHECK-NOT: sxtb
230 ; CHECK-NOT: sxtb
319 ; CHECK-NOT: sxtb
341 ; CHECK-NOT: sxtb
435 ; CHECK-NOT: sxtb
459 ; CHECK-NOT: sxtb
|
| D | fast-isel-int-ext3.ll | 66 ; CHECK: sxtb w0, [[REG]]
88 ; CHECK: sxtb x0, [[REG]]
|
| D | arm64-narrow-ldst-merge.ll | 139 ; CHECK-DAG: sxtb [[LO_PART:w[0-9]+]], [[NEW_DEST]]
158 ; BE-DAG: sxtb [[LO_PART:w[0-9]+]], [[NEW_DEST]]
175 ; LE-DAG: sxtb [[LO_PART:w[0-9]+]], [[NEW_DEST]]
267 ; CHECK-DAG: sxtb [[HI_PART:w[0-9]+]], [[NEW_DEST]]
284 ; LE-DAG: sxtb [[HI_PART:w[0-9]+]], [[NEW_DEST]]
305 ; BE-DAG: sxtb [[HI_PART:w[0-9]+]], [[NEW_DEST]]
|
| D | bitfield.ll | 11 ; CHECK: sxtb {{w[0-9]+}}, {{w[0-9]+}}
27 ; CHECK: sxtb {{x[0-9]+}}, {{w[0-9]+}}
144 ; CHECK: sxtb {{x[0-9]+}}, {{w[0-9]+}}
|
| D | arm64-shifted-sext.ll | 45 ; CHECK: sxtb [[REG]], [[REG]]
91 ; CHECK: sxtb [[REG]], [[REG]]
136 ; CHECK: sxtb x[[REG]], w[[REG]]
|
| /external/llvm/test/MC/ARM/ |
| D | thumb.s | 25 sxtb r2, r3
27 @ CHECK: sxtb r2, r3 @ encoding: [0x5a,0xb2]
|
| D | diagnostics.s | 312 sxtb r8, r3, #8
313 sxtb r8, r3, ror 24
314 sxtb r8, r3, ror #8 -
321 @ CHECK-ERRORS: sxtb r8, r3, #8
324 @ CHECK-ERRORS: sxtb r8, r3, ror 24
327 @ CHECK-ERRORS: sxtb r8, r3, ror #8 -
330 @ CHECK-ERRORS: sxtb r8, r3, ror #8 -
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-arithmetic.txt | 177 # CHECK: add w1, w2, w3, sxtb
192 # CHECK: add x1, x2, w3, sxtb
219 # CHECK: sub w1, w2, w3, sxtb
234 # CHECK: sub x1, x2, w3, sxtb
261 # CHECK: adds w1, w2, w3, sxtb
276 # CHECK: adds x1, x2, w3, sxtb
299 # CHECK: subs w1, w2, w3, sxtb
314 # CHECK: subs x1, x2, w3, sxtb
|
| /external/llvm/test/MC/Disassembler/Hexagon/ |
| D | alu32_pred.txt | 106 # CHECK: if (p3) r17 = sxtb(r21)
108 # CHECK: if (!p3) r17 = sxtb(r21)
111 # CHECK-NEXT: if (p3.new) r17 = sxtb(r21)
114 # CHECK-NEXT: if (!p3.new) r17 = sxtb(r21)
|
| /external/llvm/test/CodeGen/Hexagon/intrinsics/ |
| D | alu32_alu.ll | 81 declare i32 @llvm.hexagon.A2.sxtb(i32)
83 %z = call i32 @llvm.hexagon.A2.sxtb(i32 %a)
86 ; CHECK: = sxtb({{.*}})
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-sxt-uxt.ll | 12 ; CHECK: sxtb
|
| D | thumb2-sxt_rot.ll | 6 ; CHECK: sxtb r0, r0
|
| /external/libavc/common/arm/ |
| D | ih264_weighted_bi_pred_a9q.s | 143 sxtb r7, r7 @sign-extend 16-bit wt1 to 32-bit
146 sxtb r9, r9 @sign-extend 8-bit ofst1 to 32-bit
154 sxtb r8, r8 @sign-extend 16-bit wt2 to 32-bit
157 sxtb r10, r10 @sign-extend 8-bit ofst2 to 32-bit
471 sxtb r9, r9 @sign-extend 8-bit ofst1_u to 32-bit
472 sxtb r10, r10 @sign-extend 8-bit ofst2_u to 32-bit
473 sxtb r7, r7 @sign-extend 8-bit ofst1_v to 32-bit
474 sxtb r8, r8 @sign-extend 8-bit ofst2_v to 32-bit
|
| /external/llvm/test/CodeGen/Thumb/ |
| D | ldr_ext.ll | 30 ; V6: sxtb
|