Home
last modified time | relevance | path

Searched refs:tablegen (Results 1 – 25 of 250) sorted by relevance

12345678910

/external/llvm/lib/Target/AArch64/
DCMakeLists.txt3 tablegen(LLVM AArch64GenRegisterInfo.inc -gen-register-info)
4 tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info)
5 tablegen(LLVM AArch64GenMCCodeEmitter.inc -gen-emitter)
6 tablegen(LLVM AArch64GenMCPseudoLowering.inc -gen-pseudo-lowering)
7 tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
8 tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
9 tablegen(LLVM AArch64GenAsmMatcher.inc -gen-asm-matcher)
10 tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
11 tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
12 tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
[all …]
/external/llvm/lib/Target/ARM/
DCMakeLists.txt3 tablegen(LLVM ARMGenRegisterInfo.inc -gen-register-info)
4 tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
5 tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter)
6 tablegen(LLVM ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
7 tablegen(LLVM ARMGenAsmWriter.inc -gen-asm-writer)
8 tablegen(LLVM ARMGenAsmMatcher.inc -gen-asm-matcher)
9 tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel)
10 tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel)
11 tablegen(LLVM ARMGenCallingConv.inc -gen-callingconv)
12 tablegen(LLVM ARMGenSubtargetInfo.inc -gen-subtarget)
[all …]
/external/llvm/lib/Target/Mips/
DCMakeLists.txt3 tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
4 tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
5 tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler)
6 tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter)
7 tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
8 tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
9 tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel)
10 tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
11 tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
12 tablegen(LLVM MipsGenAsmMatcher.inc -gen-asm-matcher)
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DMakefile19 tablegen = $(TBLGEN) -I $(LLVM_INCLUDEDIR) $1 $2 -o $3 macro
40 $(call tablegen, -gen-register-info, AMDGPU.td, $@)
43 $(call tablegen, -gen-instr-info, AMDGPU.td, $@)
46 $(call tablegen, -gen-asm-writer, AMDGPU.td, $@)
49 $(call tablegen, -gen-dag-isel, AMDGPU.td, $@)
52 $(call tablegen, -gen-callingconv, AMDGPU.td, $@)
55 $(call tablegen, -gen-subtarget, AMDGPU.td, $@)
58 $(call tablegen, -gen-enhanced-disassembly-info, AMDGPU.td, $@)
61 $(call tablegen, -gen-tgt-intrinsic, AMDGPU.td, $@)
64 $(call tablegen, -gen-emitter, AMDGPU.td, $@)
[all …]
/external/llvm/lib/Target/X86/
DCMakeLists.txt3 tablegen(LLVM X86GenRegisterInfo.inc -gen-register-info)
4 tablegen(LLVM X86GenDisassemblerTables.inc -gen-disassembler)
5 tablegen(LLVM X86GenInstrInfo.inc -gen-instr-info)
6 tablegen(LLVM X86GenAsmWriter.inc -gen-asm-writer)
7 tablegen(LLVM X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
8 tablegen(LLVM X86GenAsmMatcher.inc -gen-asm-matcher)
9 tablegen(LLVM X86GenDAGISel.inc -gen-dag-isel)
10 tablegen(LLVM X86GenFastISel.inc -gen-fast-isel)
11 tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)
12 tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget)
/external/llvm/lib/Target/Sparc/
DCMakeLists.txt3 tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info)
4 tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info)
5 tablegen(LLVM SparcGenDisassemblerTables.inc -gen-disassembler)
6 tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter)
7 tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer)
8 tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher)
9 tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel)
10 tablegen(LLVM SparcGenSubtargetInfo.inc -gen-subtarget)
11 tablegen(LLVM SparcGenCallingConv.inc -gen-callingconv)
/external/llvm/lib/Target/PowerPC/
DCMakeLists.txt3 tablegen(LLVM PPCGenAsmWriter.inc -gen-asm-writer)
4 tablegen(LLVM PPCGenAsmMatcher.inc -gen-asm-matcher)
5 tablegen(LLVM PPCGenDisassemblerTables.inc -gen-disassembler)
6 tablegen(LLVM PPCGenMCCodeEmitter.inc -gen-emitter)
7 tablegen(LLVM PPCGenRegisterInfo.inc -gen-register-info)
8 tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info)
9 tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel)
10 tablegen(LLVM PPCGenFastISel.inc -gen-fast-isel)
11 tablegen(LLVM PPCGenCallingConv.inc -gen-callingconv)
12 tablegen(LLVM PPCGenSubtargetInfo.inc -gen-subtarget)
/external/llvm/lib/Target/Hexagon/
DCMakeLists.txt3 tablegen(LLVM HexagonGenAsmMatcher.inc -gen-asm-matcher)
4 tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
5 tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
6 tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
7 tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer)
8 tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
9 tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
10 tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
11 tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
12 tablegen(LLVM HexagonGenSubtargetInfo.inc -gen-subtarget)
DHexagonSchedule.td1 //===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===//
/external/llvm/lib/Target/SystemZ/
DCMakeLists.txt3 tablegen(LLVM SystemZGenAsmMatcher.inc -gen-asm-matcher)
4 tablegen(LLVM SystemZGenAsmWriter.inc -gen-asm-writer)
5 tablegen(LLVM SystemZGenCallingConv.inc -gen-callingconv)
6 tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel)
7 tablegen(LLVM SystemZGenDisassemblerTables.inc -gen-disassembler)
8 tablegen(LLVM SystemZGenMCCodeEmitter.inc -gen-emitter)
9 tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info)
10 tablegen(LLVM SystemZGenRegisterInfo.inc -gen-register-info)
11 tablegen(LLVM SystemZGenSubtargetInfo.inc -gen-subtarget)
/external/llvm/lib/Target/AMDGPU/
DCMakeLists.txt3 tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
4 tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
5 tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
6 tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
7 tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
8 tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)
9 tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
10 tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
11 tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
12 tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
/external/llvm/lib/Target/BPF/
DCMakeLists.txt3 tablegen(LLVM BPFGenRegisterInfo.inc -gen-register-info)
4 tablegen(LLVM BPFGenInstrInfo.inc -gen-instr-info)
5 tablegen(LLVM BPFGenAsmWriter.inc -gen-asm-writer)
6 tablegen(LLVM X86GenAsmMatcher.inc -gen-asm-matcher)
7 tablegen(LLVM BPFGenDAGISel.inc -gen-dag-isel)
8 tablegen(LLVM BPFGenMCCodeEmitter.inc -gen-emitter)
9 tablegen(LLVM BPFGenCallingConv.inc -gen-callingconv)
10 tablegen(LLVM BPFGenSubtargetInfo.inc -gen-subtarget)
/external/llvm/lib/Target/XCore/
DCMakeLists.txt3 tablegen(LLVM XCoreGenRegisterInfo.inc -gen-register-info)
4 tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info)
5 tablegen(LLVM XCoreGenDisassemblerTables.inc -gen-disassembler)
6 tablegen(LLVM XCoreGenAsmWriter.inc -gen-asm-writer)
7 tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel)
8 tablegen(LLVM XCoreGenCallingConv.inc -gen-callingconv)
9 tablegen(LLVM XCoreGenSubtargetInfo.inc -gen-subtarget)
/external/llvm/lib/Target/WebAssembly/
DCMakeLists.txt3 tablegen(LLVM WebAssemblyGenAsmWriter.inc -gen-asm-writer)
4 tablegen(LLVM WebAssemblyGenDAGISel.inc -gen-dag-isel)
5 tablegen(LLVM WebAssemblyGenFastISel.inc -gen-fast-isel)
6 tablegen(LLVM WebAssemblyGenInstrInfo.inc -gen-instr-info)
7 tablegen(LLVM WebAssemblyGenMCCodeEmitter.inc -gen-emitter)
8 tablegen(LLVM WebAssemblyGenRegisterInfo.inc -gen-register-info)
9 tablegen(LLVM WebAssemblyGenSubtargetInfo.inc -gen-subtarget)
/external/llvm/lib/Target/MSP430/
DCMakeLists.txt3 tablegen(LLVM MSP430GenRegisterInfo.inc -gen-register-info)
4 tablegen(LLVM MSP430GenInstrInfo.inc -gen-instr-info)
5 tablegen(LLVM MSP430GenAsmWriter.inc -gen-asm-writer)
6 tablegen(LLVM MSP430GenDAGISel.inc -gen-dag-isel)
7 tablegen(LLVM MSP430GenCallingConv.inc -gen-callingconv)
8 tablegen(LLVM MSP430GenSubtargetInfo.inc -gen-subtarget)
/external/llvm/lib/Target/NVPTX/
DCMakeLists.txt4 tablegen(LLVM NVPTXGenRegisterInfo.inc -gen-register-info)
5 tablegen(LLVM NVPTXGenInstrInfo.inc -gen-instr-info)
6 tablegen(LLVM NVPTXGenAsmWriter.inc -gen-asm-writer)
7 tablegen(LLVM NVPTXGenDAGISel.inc -gen-dag-isel)
8 tablegen(LLVM NVPTXGenSubtargetInfo.inc -gen-subtarget)
/external/llvm/utils/jedit/
DREADME5 * tablegen.xml
10 <MODE NAME="tablegen" FILE="tablegen.xml" FILE_NAME_GLOB="*.td" />
/external/llvm/cmake/modules/
DTableGen.cmake5 function(tablegen project ofn) function
27 # Generate tablegen output in a temporary file.
59 # Creates a target for publicly exporting tablegen dependencies.
62 message(FATAL_ERROR "Requires tablegen() definitions as TABLEGEN_OUTPUT.")
131 add_custom_target(${project}-tablegen-host DEPENDS ${${project}_TABLEGEN_EXE})
132 set(${project}_TABLEGEN_TARGET ${project}-tablegen-host PARENT_SCOPE)
/external/llvm/include/llvm/IR/
DCMakeLists.txt2 tablegen(LLVM Attributes.inc -gen-attrs)
5 tablegen(LLVM Intrinsics.gen -gen-intrinsic)
/external/llvm/lib/Target/AVR/
DCMakeLists.txt3 tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
4 tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
/external/llvm/utils/emacs/
DREADME15 * tablegen-mode.el
22 (require 'tablegen-mode)
/external/llvm/utils/vim/ftdetect/
Dtablegen.vim1 au BufRead,BufNewFile *.td set filetype=tablegen
/external/clang/include/clang/Driver/
DCMakeLists.txt2 tablegen(LLVM Options.inc -gen-opt-parser-defs)
/external/llvm/lib/LibDriver/
DCMakeLists.txt2 tablegen(LLVM Options.inc -gen-opt-parser-defs)
/external/llvm/unittests/Option/
DCMakeLists.txt8 tablegen(LLVM Opts.inc -gen-opt-parser-defs)

12345678910