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/external/llvm/utils/emacs/
DREADME6 * llvm-mode.el
8 Syntax highlighting mode for LLVM assembly files. To use, add this code to
13 (require 'llvm-mode)
15 * tablegen-mode.el
17 Syntax highlighting mode for TableGen description files. To use, add this code
22 (require 'tablegen-mode)
/external/llvm/utils/jedit/
DREADME5 * tablegen.xml
7 Syntax highlighting mode for TableGen description files. To use, copy this
10 <MODE NAME="tablegen" FILE="tablegen.xml" FILE_NAME_GLOB="*.td" />
/external/llvm/utils/vim/
DREADME4 tablegen *.td files. It comes with filetype detection rules in the (ftdetect),
19 " LLVM Makefile highlighting mode
Dvimrc82 " Enable syntax highlighting for tablegen files. To use, copy
83 " utils/vim/tablegen.vim to ~/.vim/syntax .
85 au! BufRead,BufNewFile *.td set filetype=tablegen
116 " In findstart mode, look for the beginning of the current identifier.
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILBase.td1 //===- AMDIL.td - AMDIL Target Machine -------------*- tablegen -*-===//
66 "Debug mode is enabled, so disable hardware accelerated address spaces.">;
DAMDILInstrInfo.td1 //===------------ AMDILInstrInfo.td - AMDIL Target ------*-tablegen-*------===//
154 // Complex addressing mode patterns
/external/llvm/lib/Target/Sparc/
DSparc.td1 //===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===//
28 "Enable deprecated V8 instructions in V9 mode">;
DSparcRegisterInfo.td1 //===-- SparcRegisterInfo.td - Sparc Register defs ---------*- tablegen -*-===//
283 // Register class for 64-bit mode, with a 64-bit spill slot size.
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrControl.td1 //===- WebAssemblyInstrControl.td-WebAssembly control-flow ------*- tablegen -*-
42 // jump tables, so in practice we don't ever use TABLESWITCH_I64 in wasm32 mode
/external/llvm/lib/Target/Mips/
DMipsCallingConv.td1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
65 // tablegen-erated code.
102 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
103 // in D0 and D1 in FP32bit mode.
189 // whether the result was originally an f128 into the tablegen-erated code.
225 // Single fp arguments are passed in pairs within 32-bit mode
370 // whether the argument was originally an f128 into the tablegen-erated code.
DMips.td1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
31 // Predicate for marking the instruction as usable in hard-float mode only.
152 "Mips16 mode">;
166 "microMips mode">;
DMipsInstrFPU.td1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
23 // - 32 32-bit registers (within single-only mode)
97 // single precision in 32 32bit fp registers in SingleOnly mode
413 // Base register + offset register addressing mode (indicated by "x" in the
DMipsRegisterInfo.td1 //===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
170 /// Mips Double point precision FPU Registers in MFP64 mode.
356 // * FGR32 - 32 32-bit registers (single float only mode)
/external/llvm/
DMakefile.config.in136 # tablegen call if we're cross-compiling).
139 # Compilers for the build platflorm (mainly for tablegen
255 # When ENABLE_CXX1Y is enabled, LLVM uses c++1y mode by default to build.
259 # When ENABLE_SPLIT_DWARF is enabled, LLVM uses -gfission to build in debug mode.
/external/clang/
DCMakeLists.txt28 "--assertion-mode"
313 # clang_tablegen output-file [tablegen-arg ...] SOURCE source-file
318 # tblgen source-file -o=output-file tablegen-arg ...
331 tablegen(CLANG ${CTG_UNPARSED_ARGUMENTS})
532 # All targets below may depend on all tablegen'd files.
/external/llvm/lib/Target/X86/
DX86.td1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26 "32-bit mode (80386)">;
27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28 "16-bit mode (i8086)">;
88 // without disabling 64-bit mode.
DX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
319 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
324 // 64-bit mode. The main complication is that they cannot be encoded in an
399 // mode to prevent encoding using the 0x90 NOP encoding. xchg %eax, %eax needs
DX86InstrControl.td1 //===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===//
117 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
/external/llvm/lib/Target/ARM/
DARMScheduleV6.td1 //===-- ARMScheduleV6.td - ARM v6 Scheduling Definitions ---*- tablegen -*-===//
192 // RunFast mode so that NFP pipeline is used for single-precision when
DARM.td1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
34 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
35 "Thumb mode">;
55 "Does not support ARM mode execution",
74 "Enable divide instructions in ARM mode">;
DARMRegisterInfo.td1 //===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===//
173 // Special Registers - only available in privileged mode.
196 // For Thumb1 mode, we don't want to allocate hi regs at all, as we don't
248 // The high registers in thumb mode, R8-R15.
/external/llvm/lib/Target/Hexagon/
DHexagonInstrFormats.td1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
45 def NoAddrMode : AddrModeType<0>; // No addressing mode
46 def Absolute : AddrModeType<1>; // Absolute addressing mode
47 def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
51 def PostInc : AddrModeType<6>; // Post increment addressing mode
160 // Addressing mode for load/store instructions.
/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td1 //=- AArch64InstrAtomics.td - AArch64 Atomic codegen support -*- tablegen -*-=//
24 // When they're actually atomic, only one addressing mode (GPR64sp) is
107 // When they're actually atomic, only one addressing mode (GPR64sp) is
/external/llvm/lib/Target/SystemZ/
DSystemZInstrFormats.td1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
153 // bits<4> Mn : mode value for operand n
1004 AddressingMode mode = bdxaddr12only>
1005 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1007 [(operator cls:$R1, mode:$XBD2)]> {
1016 AddressingMode mode = bdxaddr20only>
1017 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1019 [(operator cls:$R1, mode:$XBD2)]> {
1113 AddressingMode mode = bdaddr20only>
1114 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3),
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td1 //===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===//
221 // FP rounding mode: bits 30 and 31 of the FP status and control register

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