Home
last modified time | relevance | path

Searched +refs:tablegen +refs:mode +refs:map (Results 1 – 8 of 8) sorted by relevance

/external/llvm/lib/Target/X86/
DX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
238 // Floating point stack registers. These don't map one-to-one to the FP
319 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
324 // 64-bit mode. The main complication is that they cannot be encoded in an
399 // mode to prevent encoding using the 0x90 NOP encoding. xchg %eax, %eax needs
DX86InstrFormats.td1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
124 // Class specifying the opcode map.
145 // Operand size for encodings that change based on mode.
150 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
151 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
153 // Address size for encodings that change based on mode.
249 // based on operand size of the mode?
252 // based on address size of the mode?
257 Map OpMap = OB; // Which opcode map does this inst have?
918 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
[all …]
/external/clang/docs/
DInternalsManual.rst110 you to map almost any diagnostic to the output level that you want. The only
430 mentioned, the diagnostic machinery goes through some filtering to map a
444 mode. Instead of formatting and printing out the diagnostics, this
448 documentation for the ``-verify`` mode can be found in the Clang API
522 To map from this representation to a character-based representation, the "last"
599 not reading in "raw" mode) this contains a pointer to the unique hash value
731 * The lexer can operate in "raw" mode. This mode has several features that
734 This mode is used for lexing within an "``#if 0``" block, for example.
736 support the ``-C`` preprocessor mode, which passes comments through, and is
738 * The lexer can be in ``ParsingFilename`` mode, which happens when
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
278 AssemblerPredicate<"!ModeThumb", "arm-mode">;
400 // Operands that are part of a memory addressing mode.
1840 /// mode). Used mostly in ARM and Thumb-1 modes.
1937 bits<5> mode;
1943 let Inst{17} = M; // Enabled if mode is set;
1947 let Inst{4-0} = mode;
1952 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1953 "$imod\t$iflags, $mode">;
1954 let mode = 0, M = 0 in
[all …]
DARMInstrThumb2.td1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
1386 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1510 // pseudos map between the two.
1530 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1613 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
2044 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
3685 bits<5> mode;
3692 let Inst{4-0} = mode;
3697 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3698 "$imod\t$iflags, $mode">;
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV4.td1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
392 // Template class for load instructions with Absolute set addressing mode.
536 // base + register offset addressing mode
560 // base + register offset addressing mode
595 // addressing mode
684 // Template class for store instructions with Absolute set addressing mode.
853 // base + register offset addressing mode
882 // base + register offset addressing mode
920 // base + register offset addressing mode
946 // base + register offset addressing mode
[all …]
/external/llvm/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
110 // is invalid for this mode/flavour.
301 // is invalid for this mode/flavour.
492 /// Which instruction it expands to and how the operands map from the
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
1302 // Thus, it is safe to directly map the vector loads with interesting
1470 // Thus, it is safe to directly map the vector loads with interesting
1739 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1912 // FIXME: Use dedicated range-checked addressing mode operand here.
5291 // In big endian mode every memory access has an implicit byte swap. LDR and