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Searched refs:tlt (Results 1 – 25 of 49) sorted by relevance

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/external/llvm/test/MC/Mips/
Dmips-control-instructions.s29 # CHECK32: tlt $zero, $3 # encoding: [0x00,0x03,0x00,0x32]
30 # CHECK32: tlt $zero, $3, 31 # encoding: [0x00,0x03,0x07,0xf2]
62 # CHECK64: tlt $zero, $3 # encoding: [0x00,0x03,0x00,0x32]
63 # CHECK64: tlt $zero, $3, 31 # encoding: [0x00,0x03,0x07,0xf2]
98 tlt $0,$3
99 tlt $0,$3,31
Dmicromips-trap-instructions.s15 # CHECK-EL: tlt $8, $9 # encoding: [0x28,0x01,0x3c,0x08]
30 # CHECK-EB: tlt $8, $9 # encoding: [0x01,0x28,0x08,0x3c]
42 tlt $8, $9, 0
/external/llvm/test/MC/Mips/mips2/
Dvalid.s161 … tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
162 … tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
/external/llvm/test/MC/Mips/mips32/
Dvalid.s191 … tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
192 … tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
/external/llvm/test/MC/Mips/micromips32r6/
Dinvalid.s64 tlt $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
65 tlt $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
66 …tlt $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran…
76 tlt $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dvalid.s220 tlt $15, $13 # CHECK: tlt $15, $13 # encoding: [0x01,0xaf,0x08,0x3c]
221 tlt $2, $19, 15 # CHECK: tlt $2, $19, 15 # encoding: [0x02,0x62,0xf8,0x3c]
/external/llvm/test/MC/Mips/mips3/
Dvalid.s225 … tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
226 … tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
/external/llvm/test/MC/Mips/mips32r3/
Dvalid.s228 … tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
229 … tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s228 … tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
229 … tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
/external/llvm/test/MC/Mips/mips32r5/
Dvalid.s229 … tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
230 … tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
/external/llvm/test/MC/Mips/micromips64r6/
Dinvalid.s89 tlt $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
90 tlt $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
91 …tlt $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran…
101 tlt $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dvalid.s106 tlt $15, $13 # CHECK: tlt $15, $13 # encoding: [0x01,0xaf,0x08,0x3c]
107 tlt $2, $19, 15 # CHECK: tlt $2, $19, 15 # encoding: [0x02,0x62,0xf8,0x3c]
/external/llvm/test/MC/Mips/mips5/
Dvalid.s256 … tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
257 … tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
/external/llvm/test/MC/Mips/mips64/
Dvalid.s275 … tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
276 … tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
/external/llvm/test/MC/Mips/mips4/
Dvalid.s254 … tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
255 … tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s301 … tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
302 … tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
/external/llvm/test/MC/Mips/mips64r5/
Dvalid.s302 … tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
303 … tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
/external/llvm/test/MC/Mips/mips64r3/
Dvalid.s301 … tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
302 … tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips2.s37 …tlt $15,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
38 …tlt $2,$19,133 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/MC/Disassembler/Mips/mips2/
Dvalid-mips2-el.txt150 0x32 0x00 0xed 0x01 # CHECK: tlt $15, $13
151 0x72 0x21 0x53 0x00 # CHECK: tlt $2, $19, 133
Dvalid-mips2.txt29 0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133
49 0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13
/external/llvm/test/MC/Disassembler/Mips/mips32r6/
Dvalid-mips32r6-el.txt137 0x32 0x00 0xed 0x01 # CHECK: tlt $15, $13
138 0x72 0x21 0x53 0x00 # CHECK: tlt $2, $19, 133
Dvalid-mips32r6.txt8 0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133
30 0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13
/external/llvm/test/MC/Disassembler/Mips/mips64r6/
Dvalid-mips64r6-el.txt167 0x32 0x00 0xed 0x01 # CHECK: tlt $15, $13
168 0x72 0x21 0x53 0x00 # CHECK: tlt $2, $19, 133
/external/llvm/test/MC/Disassembler/Mips/micromips64r6/
Dvalid.txt125 0x01 0xaf 0x08 0x3c # CHECK: tlt $15, $13
126 0x02 0x62 0xf8 0x3c # CHECK: tlt $2, $19, 15

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