| /external/llvm/test/MC/AArch64/ |
| D | neon-scalar-shift-imm.s | 157 uqrshrn b10, h12, #5
158 uqrshrn h12, s10, #14
159 uqrshrn s10, d10, #25
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| D | neon-simd-shift.s | 385 uqrshrn v0.8b, v1.8h, #3
386 uqrshrn v0.4h, v1.4s, #3
387 uqrshrn v0.2s, v1.2d, #3
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| D | arm64-advsimd.s | 1382 uqrshrn b0, h0, #1
1383 uqrshrn h0, s0, #2
1384 uqrshrn s0, d0, #3
1431 ; CHECK: uqrshrn b0, h0, #1 ; encoding: [0x00,0x9c,0x0f,0x7f]
1432 ; CHECK: uqrshrn h0, s0, #2 ; encoding: [0x00,0x9c,0x1e,0x7f]
1433 ; CHECK: uqrshrn s0, d0, #3 ; encoding: [0x00,0x9c,0x3d,0x7f]
1569 uqrshrn.8b v0, v0, #1
1571 uqrshrn.4h v0, v0, #3
1573 uqrshrn.2s v0, v0, #5
1741 ; CHECK: uqrshrn.8b v0, v0, #1 ; encoding: [0x00,0x9c,0x0f,0x2f]
[all …]
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| D | neon-diagnostics.s | 2010 uqrshrn v0.8b, v1.8b, #3
2011 uqrshrn v0.4h, v1.4h, #3
2012 uqrshrn v0.2s, v1.2s, #3
5149 uqrshrn b10, h12, #99
5150 uqrshrn h12, s10, #99
5151 uqrshrn s10, d10, #99
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-simd-shift.ll | 534 %vqrshrn = tail call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %b, i32 3)
545 %vqrshrn = tail call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %b, i32 9)
557 %vqrshrn = tail call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> %b, i32 19)
602 declare <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32)
604 declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32)
606 declare <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64>, i32)
|
| D | arm64-vshift.ll | 1008 ; CHECK: uqrshrn {{s[0-9]+}}, d0, #1
1009 %tmp = call i32 @llvm.aarch64.neon.uqrshrn.i32(i64 %A, i32 1)
1015 ;CHECK: uqrshrn.8b v0, {{v[0-9]+}}, #1
1017 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
1023 ;CHECK: uqrshrn.4h v0, {{v[0-9]+}}, #1
1025 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
1031 ;CHECK: uqrshrn.2s v0, {{v[0-9]+}}, #1
1033 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
1042 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
1052 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
[all …]
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 1835 # CHECK: uqrshrn b0, h0, #7
1836 # CHECK: uqrshrn h0, s0, #14
1837 # CHECK: uqrshrn s0, d0, #29
2144 # CHECK: uqrshrn.8b v0, v0, #7
2146 # CHECK: uqrshrn.4h v0, v0, #13
2148 # CHECK: uqrshrn.2s v0, v0, #27
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| D | neon-instructions.txt | 1066 # CHECK: uqrshrn v0.8b, v1.8h, #3
1067 # CHECK: uqrshrn v0.4h, v1.4s, #3
1068 # CHECK: uqrshrn v0.2s, v1.2d, #3
1948 # CHECK: uqrshrn b10, h12, #5
1949 # CHECK: uqrshrn h12, s10, #14
1950 # CHECK: uqrshrn s10, d10, #25
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| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 28118 uqrshrn s2, d5, #1 0ee40cc0dd6c5aaba55f46f4718c2e26 5a3fe491ea9abedf84c2d203e0deea0b 0000000000…
28119 uqrshrn s2, d5, #17 8f670bc127b737083ccd153b549870b8 7b1a19f206ab2014f8998d1302b0164e 000000000…
28120 uqrshrn s2, d5, #32 733f26155eca2a58aa5456f858f0dd22 974342dc28faeff5db8291d05e45c421 000000000…
28121 uqrshrn h2, s5, #1 1b4cbd9ae283937d50d4660bde72d544 0e98c031af688d628e5b3c1b537d5563 0000000000…
28122 uqrshrn h2, s5, #9 e66e313114c4d3558e2da75445ffb6fe 41faf2d0fbd5593a7005f0d5413828f6 0000000000…
28123 uqrshrn h2, s5, #16 3484e1ba546b49c2c23e79b2ed77e22f 8f4838986d21b45ee1600ddc89569eb9 000000000…
28124 uqrshrn b2, h5, #1 5964f36b642cfdae424cf2108ab7168b 724b9d77dec1a2a4738e8453161e9224 0000000000…
28125 uqrshrn b2, h5, #4 fe2d822740d6950bf3a8ff53a43af14d edba28b1639d241676e182bc8615fc16 0000000000…
28126 uqrshrn b2, h5, #8 de8245ad62feda525256958438c18de0 3baebfec4570ac2cc17ee14b8787808f 0000000000…
28182 uqrshrn v4.2s, v29.2d, #1 32c8425f488028baf4761aba3a1a5f3b 1489d76dbea237c4e69158afbea06b0f 0…
[all …]
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| /external/vixl/test/ |
| D | test-simulator-a64.cc | 3896 DEFINE_TEST_NEON_2OPIMM_NARROW(uqrshrn, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
3926 DEFINE_TEST_NEON_2OPIMM_SCALAR_NARROW(uqrshrn, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
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| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.cc | 3677 case NEON_UQRSHRN_scalar: uqrshrn(vf, rd, rn, right_shift); break; in VisitNEONScalarShiftImmediate()
3785 uqrshrn(vf, rd, rn, right_shift); in VisitNEONShiftImmediate()
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| D | simulator-a64.h | 2102 LogicVRegister uqrshrn(VectorFormat vform,
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| D | macro-assembler-a64.h | 2423 V(uqrshrn, Uqrshrn) \
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| D | assembler-a64.h | 3327 void uqrshrn(const VRegister& vd,
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| D | logic-a64.cc | 2673 LogicVRegister Simulator::uqrshrn(VectorFormat vform, in uqrshrn() function in vixl::Simulator
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| D | assembler-a64.cc | 4499 void Assembler::uqrshrn(const VRegister& vd, in uqrshrn() function in vixl::Assembler
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| /external/vixl/doc/ |
| D | supported-instructions.md | 4375 void uqrshrn(const VRegister& vd,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4638 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4694 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
|