| /external/llvm/test/MC/AArch64/ |
| D | neon-scalar-shift-imm.s | 135 uqshrn b12, h10, #7
136 uqshrn h10, s14, #5
137 uqshrn s10, d12, #13
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| D | neon-simd-shift.s | 350 uqshrn v0.8b, v1.8h, #3
351 uqshrn v0.4h, v1.4s, #3
352 uqshrn v0.2s, v1.2d, #3
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| D | arm64-advsimd.s | 1389 uqshrn b0, h0, #1
1390 uqshrn h0, s0, #2
1391 uqshrn s0, d0, #3
1438 ; CHECK: uqshrn b0, h0, #1 ; encoding: [0x00,0x94,0x0f,0x7f]
1439 ; CHECK: uqshrn h0, s0, #2 ; encoding: [0x00,0x94,0x1e,0x7f]
1440 ; CHECK: uqshrn s0, d0, #3 ; encoding: [0x00,0x94,0x3d,0x7f]
1582 uqshrn.8b v0, v0, #1
1584 uqshrn.4h v0, v0, #3
1586 uqshrn.2s v0, v0, #5
1754 ; CHECK: uqshrn.8b v0, v0, #1 ; encoding: [0x00,0x94,0x0f,0x2f]
[all …]
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| D | neon-diagnostics.s | 1952 uqshrn v0.8b, v1.8b, #3
1953 uqshrn v0.4h, v1.4h, #3
1954 uqshrn v0.2s, v1.2s, #3
5113 uqshrn b12, h10, #99
5114 uqshrn h10, s14, #99
5115 uqshrn s10, d12, #99
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-simd-shift.ll | 468 %vqshrn = tail call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %b, i32 3)
479 %vqshrn = tail call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %b, i32 9)
491 %vqshrn = tail call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %b, i32 19)
590 declare <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16>, i32)
592 declare <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32>, i32)
594 declare <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64>, i32)
|
| D | arm64-vshift.ll | 1074 ; CHECK: uqshrn {{s[0-9]+}}, d0, #1
1075 %tmp = call i32 @llvm.aarch64.neon.uqshrn.i32(i64 %A, i32 1)
1081 ;CHECK: uqshrn.8b v0, {{v[0-9]+}}, #1
1083 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)
1089 ;CHECK: uqshrn.4h v0, {{v[0-9]+}}, #1
1091 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)
1097 ;CHECK: uqshrn.2s v0, {{v[0-9]+}}, #1
1099 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)
1108 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)
1118 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)
[all …]
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 1842 # CHECK: uqshrn b0, h0, #7
1843 # CHECK: uqshrn h0, s0, #14
1844 # CHECK: uqshrn s0, d0, #29
2157 # CHECK: uqshrn.8b v0, v0, #7
2159 # CHECK: uqshrn.4h v0, v0, #13
2161 # CHECK: uqshrn.2s v0, v0, #27
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| D | neon-instructions.txt | 1034 # CHECK: uqshrn v0.8b, v1.8h, #3
1035 # CHECK: uqshrn v0.4h, v1.4s, #3
1036 # CHECK: uqshrn v0.2s, v1.2d, #3
1928 # CHECK: uqshrn b12, h10, #7
1929 # CHECK: uqshrn h10, s14, #5
1930 # CHECK: uqshrn s10, d12, #13
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| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 28136 uqshrn s2, d5, #1 323ed327aa3bdfbc80c6c8864fe3d6fc 480a49c8d8a23de5f13567da1f60b9e3 00000000000…
28137 uqshrn s2, d5, #17 55a7b3384f6a6d9c9b440b75505d3d0c 87b87b430bc1ace9e589311e9b4ce570 0000000000…
28138 uqshrn s2, d5, #32 cc151fcad21082a17e8c2e0b61d13e23 b262117934d0faca399db34140aa03bd 0000000000…
28139 uqshrn h2, s5, #1 f66877be920c7ea9897c9226e4213923 28e96b48b3ad86664d534e206e5b74a9 00000000000…
28140 uqshrn h2, s5, #9 34801cf4ef40bf951af596a8392b8eea f82c196d376469a7347b2275f04d293f 00000000000…
28141 uqshrn h2, s5, #16 760eed353055d95231204c9ae736cde2 46af842ab4ee284d0585eab3b2731a96 0000000000…
28143 uqshrn b2, h5, #1 0e6cd512eedf6062c2f870f4f22075ee 98a7ac58bf5f9d074dc8c3873605d6e5 00000000000…
28144 uqshrn b2, h5, #4 7127010982b8a5ae93f12c8b06ddef1a 4df4f0d9b79629b46c240cd1dbe1bc0c 00000000000…
28145 uqshrn b2, h5, #8 c676b08bfd752c36c379267102e92ceb 5627653622eb347a55fea66c079d33c2 00000000000…
28219 uqshrn v4.2s, v29.2d, #1 f69e0f96b71dab056513223799a245fe 6e64f54607aaf431f74bb589e5a1d382 00…
[all …]
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| /external/vixl/test/ |
| D | test-simulator-a64.cc | 3895 DEFINE_TEST_NEON_2OPIMM_NARROW(uqshrn, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
3925 DEFINE_TEST_NEON_2OPIMM_SCALAR_NARROW(uqshrn, Basic, TypeWidth) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
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| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.cc | 3676 case NEON_UQSHRN_scalar: uqshrn(vf, rd, rn, right_shift); break; in VisitNEONScalarShiftImmediate()
3778 uqshrn(vf, rd, rn, right_shift); in VisitNEONShiftImmediate()
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| D | simulator-a64.h | 2094 LogicVRegister uqshrn(VectorFormat vform,
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| D | macro-assembler-a64.h | 2426 V(uqshrn, Uqshrn) \
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| D | assembler-a64.h | 3317 void uqshrn(const VRegister& vd,
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| D | logic-a64.cc | 2657 LogicVRegister Simulator::uqshrn(VectorFormat vform, in uqshrn() function in vixl::Simulator
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| D | assembler-a64.cc | 4483 void Assembler::uqshrn(const VRegister& vd, in uqshrn() function in vixl::Assembler
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| /external/vixl/doc/ |
| D | supported-instructions.md | 4411 void uqshrn(const VRegister& vd,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4641 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4697 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
|