| /external/llvm/test/CodeGen/AArch64/ |
| D | bitreverse.ll | 10 ; CHECK: ushr
62 ; CHECK-DAG: ushr [[S5:v.*]], v0.8b, #1
63 ; CHECK-DAG: ushr [[S6:v.*]], v0.8b, #3
64 ; CHECK-DAG: ushr [[S7:v.*]], v0.8b, #5
65 ; CHECK-DAG: ushr [[S8:v.*]], v0.8b, #7
|
| D | rotate.ll | 4 ;; select ROTL. Make sure if generates the basic ushr/shl.
7 ; CHECK: ushr {{v[0-9]+}}.2d
|
| D | arm64-neon-simd-shift.ll | 54 ; CHECK: ushr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #3
61 ; CHECK: ushr {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #3
68 ; CHECK: ushr {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #3
75 ; CHECK: ushr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #3
82 ; CHECK: ushr {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #3
89 ; CHECK: ushr {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #3
96 ; CHECK: ushr {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #3
|
| D | arm64-vshr.ll | 58 ; CHECK: ushr d0, d0, #63
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-shift.s | 26 ushr v0.8b, v1.8b, #3
27 ushr v0.4h, v1.4h, #3
28 ushr v0.2s, v1.2s, #3
29 ushr v0.16b, v1.16b, #3
30 ushr v0.8h, v1.8h, #3
31 ushr v0.4s, v1.4s, #3
32 ushr v0.2d, v1.2d, #3
|
| D | neon-scalar-shift-imm.s | 15 ushr d10, d17, #18
|
| D | arm64-advsimd.s | 1394 ushr d0, d0, #1 define
1443 ; CHECK: ushr d0, d0, #1 ; encoding: [0x00,0x04,0x7f,0x7f]
1608 ushr.8b v0, v0, #1
1609 ushr.16b v0, v0, #2
1610 ushr.4h v0, v0, #3
1611 ushr.8h v0, v0, #4
1612 ushr.2s v0, v0, #5
1613 ushr.4s v0, v0, #6
1614 ushr.2d v0, v0, #7
1780 ; CHECK: ushr.8b v0, v0, #1 ; encoding: [0x00,0x04,0x0f,0x2f]
[all …]
|
| D | neon-diagnostics.s | 1411 ushr v0.8b, v1.8h, #3
1412 ushr v0.4h, v1.4s, #3
1413 ushr v0.2s, v1.2d, #3
1414 ushr v0.16b, v1.16b, #9
1415 ushr v0.8h, v1.8h, #17
1416 ushr v0.4s, v1.4s, #33
1417 ushr v0.2d, v1.2d, #65
4923 ushr d10, d17, #99
|
| /external/smali/smali/src/test/resources/LexerTest/ |
| D | InstructionTest.smali | 44 ushr-int/2addr
55 ushr-long/2addr
186 ushr-int
197 ushr-long
|
| D | InstructionTest.tokens | 44 INSTRUCTION_FORMAT12x("ushr-int/2addr")
55 INSTRUCTION_FORMAT12x("ushr-long/2addr")
186 INSTRUCTION_FORMAT23x("ushr-int")
197 INSTRUCTION_FORMAT23x("ushr-long")
|
| /external/libavc/common/armv8/ |
| D | ih264_resi_trans_quant_av8.s | 238 …ushr v0.8b, v0.8b, #7 //i reduce comaparison bit to a signle bit row 1 and 2 blk …
239 …ushr v1.8b, v1.8b, #7 //i reduce comaparison bit to a signle bit row 1 and 2 blk …
461 …ushr v0.8b, v0.8b, #7 //i reduce comaparison bit to a signle bit row 1 and 2 blk …
462 …ushr v1.8b, v1.8b, #7 //i reduce comaparison bit to a signle bit row 1 and 2 blk …
612 ushr v2.8b, v2.8b, #7
613 ushr v3.8b, v3.8b, #7
715 ushr v5.8b, v5.8b, #7 //reduce nnz comparison to 1 bit
|
| /external/smali/smali/src/main/jflex/ |
| D | smaliLexer.jflex | 445 …"or-int/2addr" | "xor-int/2addr" | "shl-int/2addr" | "shr-int/2addr" | "ushr-int/2addr" | "add-lon…
447 "xor-long/2addr" | "shl-long/2addr" | "shr-long/2addr" | "ushr-long/2addr" | "add-float/2addr" |
504 "or-int/lit8" | "xor-int/lit8" | "shl-int/lit8" | "shr-int/lit8" | "ushr-int/lit8" {
551 …"or-int" | "xor-int" | "shl-int" | "shr-int" | "ushr-int" | "add-long" | "sub-long" | "mul-long" |…
552 …"rem-long" | "and-long" | "or-long" | "xor-long" | "shl-long" | "shr-long" | "ushr-long" | "add-fl…
|
| /external/mesa3d/src/gallium/state_trackers/d3d1x/d3d1xshader/defs/ |
| D | opcodes.txt | 86 ushr
|
| /external/boringssl/linux-aarch64/crypto/modes/ |
| D | ghashv8-armx64.S | 16 ushr v18.2d,v19.2d,#63
19 ushr v18.2d,v3.2d,#63
|
| /external/icu/icu4c/source/test/intltest/ |
| D | itrbnf.cpp | 718 LLAssert(llong(0x7fffa0a0, 0xbcbcdfdf).ushr(16) == llong(0x7fff,0xa0a0bcbc));
719 LLAssert(llong(0x8000789a, 0xbcde0000).ushr(16) == llong(0x00008000,0x789abcde));
720 LLAssert(llong(0x80000000, 0).ushr(63) == llong(0, 1));
721 LLAssert(llong(0x80000000, 0).ushr(47) == llong(0, 0x10000));
722 …LLAssert(llong(0x80000000, 0x80000000).ushr(64) == llong(0x80000000, 0x80000000)); // only lower 6…
723 LLAssert(llong(0x80000000, 0).ushr(-1) == llong(0, 1)); // only lower 6 bits are used
|
| /external/libhevc/common/arm64/ |
| D | ihevc_intra_pred_luma_dc.s | 212 ushr v29.4h, v27.4h,#2 //final dst[0]'s value in d15[0]
457 ushr v29.4h, v27.4h,#2 //final dst[0]'s value in d15[0]
|
| D | ihevc_deblk_luma_vert.s | 526 ushr v16.8h,v16.8h,#1
584 ushr v2.8h,v2.8h,#1
|
| /external/libmpeg2/common/armv8/ |
| D | ideint_cac_av8.s | 211 ushr v0.2s, v21.2s, #3
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.c | 4143 GEN_SHIFT_TEST(ushr, 2d, 2d, 1)
4144 GEN_SHIFT_TEST(ushr, 2d, 2d, 13)
4145 GEN_SHIFT_TEST(ushr, 2d, 2d, 64)
4146 GEN_SHIFT_TEST(ushr, 4s, 4s, 1)
4147 GEN_SHIFT_TEST(ushr, 4s, 4s, 13)
4148 GEN_SHIFT_TEST(ushr, 4s, 4s, 32)
4149 GEN_SHIFT_TEST(ushr, 2s, 2s, 1)
4150 GEN_SHIFT_TEST(ushr, 2s, 2s, 13)
4151 GEN_SHIFT_TEST(ushr, 2s, 2s, 32)
4152 GEN_SHIFT_TEST(ushr, 8h, 8h, 1)
[all …]
|
| D | fp_and_simd.stdout.exp | 28445 ushr d5, d28, #1 f950127543e312759be7bd65289e0798 6ec2093c8bb67575311ab44f77c664e3 000000000000…
28446 ushr d5, d28, #32 ce68707a065cac86808cd701dd5a5010 2e2e0a3cab304039bea4a5d07803c368 00000000000…
28447 ushr d5, d28, #64 36c49c40e68c0cfb6c391283e45175d0 1ad6b03602d9281aeb2e8f6ee2f455ed 00000000000…
28487 ushr v8.2d, v7.2d, #1 b539b2cd5e9cc94e8efaf600d0b9dd57 5a9cd966af4e64a7477d7b00685ceeab fpsr=0000…
28488 ushr v8.2d, v7.2d, #13 e48eb3a250b879282c53c9aec1557c92 000724759d1285c30001629e4d760aab fpsr=000…
28489 ushr v8.2d, v7.2d, #64 3b7d58a02bac2ef44df8178f2969a339 00000000000000000000000000000000 fpsr=000…
28490 ushr v8.4s, v7.4s, #1 04040e667bb4928fbf65cbc013b27fa8 020207333dda49475fb2e5e009d93fd4 fpsr=0000…
28491 ushr v8.4s, v7.4s, #13 8c1e428dcd0b51d64c17d25d8bec3c3b 000460f20006685a000260be00045f61 fpsr=000…
28492 ushr v8.4s, v7.4s, #32 1fc75eb3acee18a3c18916819dd2054e 00000000000000000000000000000000 fpsr=000…
28493 ushr v8.2s, v7.2s, #1 09fbd074a49993d3ea3784485621063d 0000000000000000751bc2242b10831e fpsr=0000…
[all …]
|
| /external/jarjar/lib/ |
| D | asm-commons-4.0.jar | ... SHL
public static final int SHR
public static final int USHR
public static final int AND
public static final int OR ... |
| /external/owasp/sanitizer/tools/findbugs/lib/ |
| D | asm-commons-3.3.jar | META-INF/MANIFEST.MF
org/objectweb/asm/commons/AdviceAdapter.class
< ... |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 1847 # CHECK: ushr d0, d0, #63
2183 # CHECK: ushr.8b v0, v0, #7
2184 # CHECK: ushr.16b v0, v0, #6
2185 # CHECK: ushr.4h v0, v0, #13
2186 # CHECK: ushr.8h v0, v0, #12
2187 # CHECK: ushr.2s v0, v0, #27
2188 # CHECK: ushr.4s v0, v0, #26
2189 # CHECK: ushr.2d v0, v0, #57
|
| D | neon-instructions.txt | 738 # CHECK: ushr v0.8b, v1.8b, #3
739 # CHECK: ushr v0.4h, v1.4h, #3
740 # CHECK: ushr v0.2s, v1.2s, #3
741 # CHECK: ushr v0.16b, v1.16b, #3
742 # CHECK: ushr v0.8h, v1.8h, #3
743 # CHECK: ushr v0.4s, v1.4s, #3
744 # CHECK: ushr v0.2d, v1.2d, #3
1822 # CHECK: ushr d10, d17, #18
|
| /external/vixl/src/vixl/a64/ |
| D | logic-a64.cc | 1756 LogicVRegister Simulator::ushr(VectorFormat vform, in ushr() function in vixl::Simulator
1793 LogicVRegister shifted_reg = ushr(vform, temp, src, shift); in usra()
1813 LogicVRegister shifted_reg = ushr(vform, temp, src, shift).Round(vform); in ursra()
2502 LogicVRegister shifted_src = ushr(vform_src, temp, src, shift); in shrn()
2514 LogicVRegister shifted_src = ushr(vformsrc, temp, src, shift); in shrn2()
2526 LogicVRegister shifted_src = ushr(vformsrc, temp, src, shift).Round(vformsrc); in rshrn()
2538 LogicVRegister shifted_src = ushr(vformsrc, temp, src, shift).Round(vformsrc); in rshrn2()
|