/external/llvm/test/MC/AArch64/ |
D | neon-3vdiff.s | 349 usubw v0.8h, v1.8h, v2.8b 350 usubw v0.4s, v1.4s, v2.4h 351 usubw v0.2d, v1.2d, v2.2s
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D | neon-diagnostics.s | 2731 usubw v0.8h, v1.8h, v2.8h 2732 usubw v0.4s, v1.4s, v2.4s 2733 usubw v0.2d, v1.2d, v2.2d
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/external/libhevc/common/arm64/ |
D | ihevc_deblk_chroma_vert.s | 148 usubw v4.8h, v0.8h , v4.8b
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/external/libavc/common/armv8/ |
D | ih264_deblk_luma_av8.s | 583 usubw v18.8h, v18.8h , v10.8b //(q2 + ((p0 + q0 + 1) >> 1) - q1) L 585 usubw v18.8h, v18.8h , v10.8b //(q2 + ((p0 + q0 + 1) >> 1) - 2*q1)L 586 usubw v20.8h, v20.8h , v11.8b //(q2 + ((p0 + q0 + 1) >> 1) - q1) H 588 usubw v20.8h, v20.8h , v11.8b //(q2 + ((p0 + q0 + 1) >> 1) - 2*q1) H 605 usubw v28.8h, v28.8h , v10.8b //((q0 - p0) << 2) + (p1 - q1) L 606 usubw v30.8h, v30.8h , v11.8b //((q0 - p0) << 2) + (p1 - q1) H
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-vsub.ll | 352 ;CHECK: usubw.8h 362 ;CHECK: usubw.4s 372 ;CHECK: usubw.2d
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D | arm64-neon-3vdiff.ll | 460 ; CHECK: usubw {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8b 469 ; CHECK: usubw {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4h 478 ; CHECK: usubw {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | neon-instructions.txt | 1412 # CHECK: usubw v0.8h, v1.8h, v2.8b 1413 # CHECK: usubw v0.4s, v1.4s, v2.4h 1414 # CHECK: usubw v0.2d, v1.2d, v2.2s
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/external/vixl/src/vixl/a64/ |
D | simulator-a64.h | 1872 LogicVRegister usubw(VectorFormat vform,
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D | macro-assembler-a64.h | 2232 V(usubw, Usubw) \
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D | assembler-a64.h | 3169 void usubw(const VRegister& vd,
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D | simulator-a64.cc | 2739 case NEON_USUBW: usubw(vf_l, rd, rn, rm); break; in VisitNEON3Different()
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D | logic-a64.cc | 2901 LogicVRegister Simulator::usubw(VectorFormat vform, in usubw() function in vixl::Simulator
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D | assembler-a64.cc | 2494 void Assembler::usubw(const VRegister& vd, in usubw() function in vixl::Assembler
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/external/vixl/test/ |
D | test-simulator-a64.cc | 3843 DEFINE_TEST_NEON_3DIFF_WIDE(usubw, Basic)
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/external/vixl/doc/ |
D | supported-instructions.md | 4577 void usubw(const VRegister& vd,
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/external/valgrind/none/tests/arm64/ |
D | fp_and_simd.stdout.exp | 27441 usubw v5.8h, v13.8h, v31.8b da01d0e5c09790e030e25518fa1e65b6 fa7cd9d076cf0bcd055b47518893a0e8 … 27443 usubw v5.4s, v13.4s, v31.4h dbde090c5f8a4261d131d618f1f4ce51 419f2ba4926e6085e364407983591b83 … 27445 usubw v5.2d, v13.2d, v31.2s 837e2a9cfec3247e2d2833c6bcb51b8a 863efcd8868bff4fd4ccac462a419435 …
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.td | 3465 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
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