| /external/llvm/test/CodeGen/ARM/ |
| D | returned-ext.ll | 16 ; CHECKELF: uxth r0, r0
22 ; CHECKT2D: uxth r0, r0
41 ; CHECKELF-NOT: uxth r0, {{r[0-9]+}}
53 ; CHECKT2D-NOT: uxth r0, {{r[0-9]+}}
88 ; CHECKELF: uxth r0, r0
90 ; CHECKELF: uxth r0, r0
94 ; CHECKT2D: uxth r0, r0
96 ; CHECKT2D: uxth r0, r0
112 ; scheduling of uxth and mov instructions below in lieu of the 'returned'
137 ; CHECKELF: uxth r0, r0
[all …]
|
| D | fast-isel-fold.ll | 25 ; ARM-NOT: uxth
28 ; THUMB-NOT: uxth
54 ; ARM-NOT: uxth
57 ; THUMB-NOT: uxth
|
| D | fast-isel-icmp.ll | 23 ; ARM: uxth r0, r0
24 ; ARM: uxth r1, r1
27 ; THUMB: uxth r0, r0
28 ; THUMB: uxth r1, r1
|
| D | dagcombine-anyexttozeroext.ll | 27 ; For now we're generating a vmov.16 and a uxth instruction.
28 ; The uxth is redundant, and we should be able to extend without
32 ; CHECK: uxth
|
| D | uxt_rot.ll | 30 ; CHECK: uxth
31 ; CHECK-NOT: uxth
|
| D | fp16-v3.ll | 12 ; CHECK-NEXT: uxth [[RREG2:r[0-9]+]], [[RREG1]]
33 ; CHECK: uxth
|
| D | fp16-args.ll | 31 ; HARD-NOT: uxth
37 ; HARD-NEXT: uxth [[REG1:r[0-9]+]], [[REG0]]
|
| D | fast-isel-ret.ll | 46 ; CHECK: uxth r0, r0
54 ; CHECK-NOT: uxth
|
| D | fast-isel-conversion.ll | 118 ; ARM: uxth r0, r0
122 ; THUMB: uxth r0, r0
164 ; ARM: uxth r0, r0
168 ; THUMB: uxth r0, r0
|
| D | ldaex-stlex.ll | 46 ; CHECK-NOT: uxth
75 ; CHECK-NOT: uxth
|
| D | extload-knownzero.ll | 14 ; CHECK-NOT: uxth
|
| D | fast-isel.ll | 86 ; THUMB: uxth
91 ; ARM: uxth
|
| D | ldstrex.ll | 48 ; CHECK-NOT: uxth
77 ; CHECK-NOT: uxth
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 171 add w1, w2, w3, uxth
180 ; CHECK: add w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x0b]
189 add x1, x2, w3, uxth
196 ; CHECK: add x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0x8b]
215 sub w1, w2, w3, uxth
224 ; CHECK: sub w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x4b]
233 sub x1, x2, w3, uxth
240 ; CHECK: sub x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0xcb]
259 adds w1, w2, w3, uxth
268 ; CHECK: adds w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x2b]
[all …]
|
| D | arm64-aliases.s | 88 cmp x2, w3, uxth #2
101 ; CHECK: cmp x2, w3, uxth #2 ; encoding: [0x5f,0x28,0x23,0xeb]
235 uxth w1, w2
240 ; CHECK: uxth w1, w2
246 uxth x1, w2
253 ; CHECK: uxth w1, w2
|
| D | basic-a64-instructions.s | 19 add x20, sp, w19, uxth
37 add w21, w15, w17, uxth
55 add x7, x11, w13, uxth #4
65 sub x20, sp, w19, uxth #4
82 sub w21, w15, w17, uxth
100 adds x20, sp, w19, uxth #4
117 adds w21, w15, w17, uxth
135 subs x20, sp, w19, uxth #4
152 subs w21, w15, w17, uxth
170 cmp sp, w19, uxth #4
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | addsub_ext.ll | 155 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
160 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
167 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
172 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
200 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, uxth
230 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
235 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
242 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
247 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
|
| D | fast-isel-int-ext2.ll | 25 ; CHECK-NOT: uxth
53 ; CHECK-NOT: uxth
166 ; CHECK-NOT: uxth
194 ; CHECK-NOT: uxth
308 ; CHECK-NOT: uxth
338 ; CHECK-NOT: uxth
|
| D | fast-isel-int-ext.ll | 164 ; CHECK-NOT: uxth
186 ; CHECK-NOT: uxth
275 ; CHECK-NOT: uxth
297 ; CHECK-NOT: uxth
387 ; CHECK-NOT: uxth
411 ; CHECK-NOT: uxth
|
| D | arm64-ldxr-stxr.ll | 52 ; CHECK-NOT: uxth
105 ; CHECK-NOT: uxth
189 ; CHECK-NOT: uxth
242 ; CHECK-NOT: uxth
|
| D | fast-isel-cbz.ll | 28 ; CHECK: uxth [[REG:w[0-9]+]], w0
|
| /external/llvm/test/MC/ARM/ |
| D | thumb.s | 34 uxth r3, r6
36 @ CHECK: uxth r3, r6 @ encoding: [0xb3,0xb2]
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-arithmetic.txt | 174 # CHECK: add w1, w2, w3, uxth
190 # CHECK: add x1, x2, w3, uxth
216 # CHECK: sub w1, w2, w3, uxth
232 # CHECK: sub x1, x2, w3, uxth
258 # CHECK: adds w1, w2, w3, uxth
274 # CHECK: adds x1, x2, w3, uxth
296 # CHECK: subs w1, w2, w3, uxth
312 # CHECK: subs x1, x2, w3, uxth
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | thumb2-sxt-uxt.ll | 19 ; CHECK: uxth
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | unpredictable-AExtI-arm.txt | 41 # CHECK: uxth
|