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Searched refs:v1024i1 (Results 1 – 8 of 8) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td122 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
123 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
127 def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
128 (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1),
132 def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))),
133 (v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1),
137 def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))),
138 (v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1),
142 def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
143 (v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
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DHexagonISelLowering.cpp204 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) { in CC_Hexagon_VarArg()
372 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) { in CC_HexagonVector()
417 (LocVT == MVT::v1024i1 && UseHVX && UseHVXDbl)) { in RetCC_Hexagon()
550 ty == MVT::v512i1 || ty == MVT::v1024i1); in IsHvxVectorType()
1110 } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) { in LowerFormalArguments()
1584 addRegisterClass(MVT::v1024i1, &Hexagon::VecPredRegs128BRegClass); in HexagonTargetLowering()
2668 case MVT::v1024i1: in getRegForInlineAsmConstraint()
DHexagonRegisterInfo.td235 def VecPredRegs128B : RegisterClass<"Hexagon", [v1024i1], 1024,
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h66 v1024i1 = 20, // 1024 x i1 enumerator
265 return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 || in is1024BitVector()
317 case v1024i1: return i1; in getVectorElementType()
368 case v1024i1: return 1024; in getVectorNumElements()
496 case v1024i1: in getSizeInBits()
593 if (NumElements == 1024) return MVT::v1024i1; in getVectorVT()
DValueTypes.td43 def v1024i1: ValueType<1024,20>; //1024 x i8 vector value
/external/llvm/lib/IR/
DValueTypes.cpp147 case MVT::v1024i1: return "v1024i1"; in getEVTString()
225 case MVT::v1024i1: return VectorType::get(Type::getInt1Ty(Context), 1024); in getTypeForEVT()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp80 case MVT::v1024i1: return "MVT::v1024i1"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td165 def llvm_v1024i1_ty : LLVMType<v1024i1>; //1024 x i1