Searched refs:v128i8 (Results 1 – 12 of 12) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 75 v128i8 = 28, //128 x i8 enumerator
265 return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 || in is1024BitVector()
325 case v128i8: in getVectorElementType()
371 case v128i8: in getVectorNumElements()
497 case v128i8: in getSizeInBits()
603 if (NumElements == 128) return MVT::v128i8; in getVectorVT()
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| D | ValueTypes.td | 52 def v128i8 : ValueType<1024,28>; //128 x i8 vector value
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 155 case MVT::v128i8: return "v128i8"; in getEVTString()
233 case MVT::v128i8: return VectorType::get(Type::getInt8Ty(Context), 128); in getTypeForEVT()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 204 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) { in CC_Hexagon_VarArg()
349 LocVT == MVT::v128i8)) { in CC_HexagonVector()
372 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) { in CC_HexagonVector()
415 } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 || in RetCC_Hexagon()
547 ty == MVT::v128i8 || in IsHvxVectorType()
886 VT == MVT::v64i16 || VT == MVT::v128i8); in getIndexedAddressParts()
1090 RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) { in LowerFormalArguments()
1098 RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) { in LowerFormalArguments()
1570 addRegisterClass(MVT::v128i8, &Hexagon::VecDblRegsRegClass); in HexagonTargetLowering()
1576 addRegisterClass(MVT::v128i8, &Hexagon::VectorRegs128BRegClass); in HexagonTargetLowering()
[all …]
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| D | HexagonRegisterInfo.td | 221 [v128i8, v64i16, v32i32, v16i64], 1024,
225 [v128i8, v64i16, v32i32, v16i64], 1024,
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| D | HexagonIntrinsicsV60.td | 132 def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))),
133 (v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1),
152 def : Pat <(v128i8 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
153 (v128i8 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
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| D | HexagonInstrInfoVector.td | 82 defm : bitconvert_dblvec<v16i64, v128i8>;
83 defm : bitconvert_dblvec<v32i32, v128i8>;
84 defm : bitconvert_dblvec<v64i16, v128i8>;
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| D | HexagonISelDAGToDAG.cpp | 415 LoadedVT == MVT::v64i16 || LoadedVT == MVT::v128i8) { in SelectIndexedLoad()
532 StoredVT == MVT::v64i16 || StoredVT == MVT::v128i8) { in SelectIndexedStore()
573 StoredVT == MVT::v64i16 || StoredVT == MVT::v128i8) in SelectIndexedStore()
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| D | HexagonInstrInfoV60.td | 780 defm : STrivv_pats <v128i8, v256i8>;
814 defm : vS32b_ai_pats <v64i8, v128i8>;
839 defm : LDrivv_pats <v128i8, v256i8>;
867 defm : vL32b_ai_pats <v64i8, v128i8>;
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| D | HexagonInstrInfo.cpp | 2292 VT == MVT::v64i16 || VT == MVT::v128i8) { in isValidAutoIncImm()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 88 case MVT::v128i8: return "MVT::v128i8"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 174 def llvm_v128i8_ty : LLVMType<v128i8>; //128 x i8
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