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Searched refs:v16f32 (Results 1 – 25 of 30) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Davx512-round.ll6 %res = call <16 x float> @llvm.floor.v16f32(<16 x float> %a)
9 declare <16 x float> @llvm.floor.v16f32(<16 x float> %p)
22 %res = call <16 x float> @llvm.ceil.v16f32(<16 x float> %a)
25 declare <16 x float> @llvm.ceil.v16f32(<16 x float> %p)
38 %res = call <16 x float> @llvm.trunc.v16f32(<16 x float> %a)
41 declare <16 x float> @llvm.trunc.v16f32(<16 x float> %p)
54 %res = call <16 x float> @llvm.rint.v16f32(<16 x float> %a)
57 declare <16 x float> @llvm.rint.v16f32(<16 x float> %p)
70 %res = call <16 x float> @llvm.nearbyint.v16f32(<16 x float> %a)
73 declare <16 x float> @llvm.nearbyint.v16f32(<16 x float> %p)
Dwide-fma-contraction.ll25 …%ret = tail call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> …
29 declare <16 x float> @llvm.fmuladd.v16f32(<16 x float>, <16 x float>, <16 x float>) nounwind readno…
Dmasked_memop.ll65 …%res = call <16 x float> @llvm.masked.load.v16f32(<16 x float>* %addr, i32 4, <16 x i1>%mask, <16 …
207 call void @llvm.masked.store.v16f32(<16 x float>%val, <16 x float>* %addr, i32 4, <16 x i1>%mask)
336 declare void @llvm.masked.store.v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)
338 declare <16 x float> @llvm.masked.load.v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)
Dmasked_gather_scatter.ll49 …%res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i…
54 declare <16 x float> @llvm.masked.gather.v16f32(<16 x float*>, i32, <16 x i1>, <16 x float>)
98 …%res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> %i…
545 …%res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i…
576 …%res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i…
604 …%res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> un…
667 …%res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> un…
1257 …%res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i…
1576 …%res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %ptrs, i32 4, <16 x i1> %mask, <…
1751 …call void @llvm.masked.scatter.v16f32(<16 x float> %src0, <16 x float*> %ptrs, i32 4, <16 x i1> %m…
[all …]
Davx512-arith.ll436 declare <16 x float> @llvm.sqrt.v16f32(<16 x float>)
442 %b = call <16 x float> @llvm.sqrt.v16f32(<16 x float> %a)
893 %t = call <16 x float> @llvm.fabs.v16f32(<16 x float> %p)
896 declare <16 x float> @llvm.fabs.v16f32(<16 x float> %p)
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h114 v16f32 = 59, // 16 x f32 enumerator
257 return (SimpleTy == MVT::v16f32 || SimpleTy == MVT::v8f64 || in is512BitVector()
356 case v16f32: return f32; in getVectorElementType()
387 case v16f32: return 16; in getVectorNumElements()
494 case v16f32: in getSizeInBits()
646 if (NumElements == 16) return MVT::v16f32; in getVectorVT()
DValueTypes.td88 def v16f32 : ValueType<512, 59>; // 16 x f32 vector value
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp122 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
123 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
124 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
125 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
149 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
150 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost()
/external/llvm/lib/Target/X86/
DX86CallingConv.td68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
122 CCIfType<[v16f32, v8f64, v16i32, v8i64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
312 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
332 CCIfType<[v16i32, v8i64, v16f32, v8f64],
372 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
415 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
490 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
507 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
526 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
DX86TargetTransformInfo.cpp552 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, in getCastInstrCost()
573 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
574 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, in getCastInstrCost()
575 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, in getCastInstrCost()
576 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
582 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
583 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, in getCastInstrCost()
584 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, in getCastInstrCost()
585 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
607 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, in getCastInstrCost()
[all …]
DX86InstrAVX512.td88 // The corresponding float type, e.g. v16f32 for v16i32
380 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
381 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
382 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
383 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
384 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
385 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
390 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
392 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
400 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
[all …]
DX86InstrFragmentsSIMD.td628 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
712 (v16f32 (alignedload512 node:$ptr))>;
870 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
/external/llvm/test/CodeGen/AMDGPU/
Dftrunc.ll10 declare <16 x float> @llvm.trunc.v16f32(<16 x float>) nounwind readnone
117 %y = call <16 x float> @llvm.trunc.v16f32(<16 x float> %x) nounwind readnone
Dfceil.ll10 declare <16 x float> @llvm.ceil.v16f32(<16 x float>) nounwind readnone
129 %y = call <16 x float> @llvm.ceil.v16f32(<16 x float> %x) nounwind readnone
Dfminnum.ll9 declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #0
117 %val = call <16 x float> @llvm.minnum.v16f32(<16 x float> %a, <16 x float> %b) #0
Dfmaxnum.ll8 declare <16 x float> @llvm.maxnum.v16f32(<16 x float>, <16 x float>) #0
118 %val = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %b) #0
/external/llvm/test/Analysis/CostModel/X86/
Dmasked-intrinsic-cost.ll77 declare void @llvm.masked.store.v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)
79 declare <16 x float> @llvm.masked.load.v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)
/external/llvm/lib/IR/
DValueTypes.cpp186 case MVT::v16f32: return "v16f32"; in getEVTString()
264 case MVT::v16f32: return VectorType::get(Type::getFloatTy(Context), 16); in getTypeForEVT()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp243 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 }, in getCastInstrCost()
244 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 }, in getCastInstrCost()
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td243 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add VGPR_512)> {
DSIISelLowering.cpp65 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass); in SITargetLowering()
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); in SITargetLowering()
205 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) { in SITargetLowering()
DAMDGPUISelLowering.cpp122 setOperationAction(ISD::STORE, MVT::v16f32, Promote); in AMDGPUTargetLowering()
123 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
162 setOperationAction(ISD::LOAD, MVT::v16f32, Promote); in AMDGPUTargetLowering()
163 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
DSIInstructions.td2548 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2551 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2599 def : BitConvert <v16i32, v16f32, VReg_512>;
2600 def : BitConvert <v16f32, v16i32, VReg_512>;
3065 defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">;
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp119 case MVT::v16f32: return "MVT::v16f32"; in getEnumName()
/external/llvm/test/Transforms/LoopVectorize/X86/
Dmasked_load_store.ll114 ;AVX512: call <16 x float> @llvm.masked.load.v16f32
116 ;AVX512: call void @llvm.masked.store.v16f32

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