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Searched refs:v16i32 (Results 1 – 25 of 32) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp135 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
136 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
137 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
555 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, in getCastInstrCost()
556 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, in getCastInstrCost()
561 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
562 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
564 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost()
565 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost()
566 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, in getCastInstrCost()
[all …]
DX86CallingConv.td68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
122 CCIfType<[v16f32, v8f64, v16i32, v8i64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
312 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
332 CCIfType<[v16i32, v8i64, v16f32, v8f64],
372 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
415 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
490 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
507 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
526 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
DX86InstrAVX512.td55 // Size of the element type in bits, e.g. 32 for v16i32.
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
88 // The corresponding float type, e.g. v16f32 for v16i32
377 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
382 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
386 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
391 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
392 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
393 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
394 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
[all …]
DX86InstrFragmentsSIMD.td632 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
714 (v16i32 (alignedload512 node:$ptr))>;
799 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
800 Mgt->getBasePtr().getValueType() == MVT::v16i32);
846 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
847 Sc->getBasePtr().getValueType() == MVT::v16i32);
867 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
DX86ISelLowering.cpp1309 addRegisterClass(MVT::v16i32, &X86::VR512RegClass); in X86TargetLowering()
1321 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal); in X86TargetLowering()
1322 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal); in X86TargetLowering()
1323 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal); in X86TargetLowering()
1324 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal); in X86TargetLowering()
1346 setOperationAction(ISD::LOAD, MVT::v16i32, Legal); in X86TargetLowering()
1367 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal); in X86TargetLowering()
1368 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal); in X86TargetLowering()
1371 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal); in X86TargetLowering()
1376 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal); in X86TargetLowering()
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h91 v16i32 = 42, // 16 x i32 enumerator
259 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 || in is512BitVector()
339 case v16i32: in getVectorElementType()
385 case v16i32: in getVectorNumElements()
492 case v16i32: in getSizeInBits()
621 if (NumElements == 16) return MVT::v16i32; in getVectorVT()
DValueTypes.td68 def v16i32 : ValueType<512, 42>; // 16 x i32 vector value
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td63 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
64 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >,
67 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
68 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >,
82 def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
83 (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1),
102 def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
103 (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1),
165 (v16i32 (V6_vandqrt (v512i1 VecPredRegs:$src1),
171 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
DHexagonISelLowering.cpp197 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_Hexagon_VarArg()
337 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_HexagonVector()
410 LocVT == MVT::v16i32 || LocVT == MVT::v8i64 || in RetCC_Hexagon()
412 LocVT = MVT::v16i32; in RetCC_Hexagon()
413 ValVT = MVT::v16i32; in RetCC_Hexagon()
436 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) { in RetCC_Hexagon()
483 if (LocVT == MVT::v16i32) { in RetCC_HexagonVector()
544 return (ty == MVT::v8i64 || ty == MVT::v16i32 || ty == MVT::v32i16 || in IsHvxVectorType()
888 UseHVX && !UseHVXDbl && (VT == MVT::v16i32 || VT == MVT::v8i64 || in getIndexedAddressParts()
1082 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 || in LowerFormalArguments()
[all …]
DHexagonInstrInfoV60.td816 defm : vS32b_ai_pats <v16i32, v32i32>;
869 defm : vL32b_ai_pats <v16i32, v32i32>;
1001 def : Pat <(v16i32 (selectcc (i32 IntRegs:$lhs), (i32 IntRegs:$rhs),
1002 (v16i32 VectorRegs:$tval),
1003 (v16i32 VectorRegs:$fval), SETEQ)),
1004 (v16i32 (VSelectPseudo_V6 (i32 (C2_cmpeq (i32 IntRegs:$lhs),
1006 (v16i32 VectorRegs:$tval),
1007 (v16i32 VectorRegs:$fval)))>;
1543 def: Pat<(v32i32 (HexagonVCOMBINE (v16i32 VectorRegs:$Vs),
1544 (v16i32 VectorRegs:$Vt))),
DHexagonInstrInfoVector.td78 defm : bitconvert_vec<v64i8, v16i32>;
79 defm : bitconvert_vec<v8i64 , v16i32>;
80 defm : bitconvert_vec<v32i16, v16i32>;
DHexagonISelDAGToDAG.cpp405 } else if (LoadedVT == MVT::v16i32 || LoadedVT == MVT::v8i64 || in SelectIndexedLoad()
526 else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 || in SelectIndexedStore()
568 else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 || in SelectIndexedStore()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp95 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
96 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
99 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
124 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
125 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp194 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
211 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
212 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
393 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 }, in getCmpSelInstrCost()
/external/llvm/test/CodeGen/X86/
Dvector-lzcnt-512.ll27 %out = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %in, i1 0)
36 %out = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %in, i1 -1)
217 declare <16 x i32> @llvm.ctlz.v16i32(<16 x i32>, i1)
Dmasked_memop.ll22 …%res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i3…
35 …%res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i3…
52 call void @llvm.masked.store.v16i32(<16 x i32>%val, <16 x i32>* %addr, i32 4, <16 x i1>%mask)
328 declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)
331 declare void @llvm.masked.store.v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)
Dvector-tzcnt-512.ll118 %out = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %in, i1 0)
132 %out = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %in, i1 -1)
269 declare <16 x i32> @llvm.cttz.v16i32(<16 x i32>, i1)
Dvector-popcnt-512.ll104 %out = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %in)
159 declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>)
Dmasked_gather_scatter.ll53 declare <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*>, i32, <16 x i1>, <16 x i32>)
131 …%res = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask…
173 …%gt1 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask…
174 …%gt2 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask…
225 …call void @llvm.masked.scatter.v16i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %i…
226 …call void @llvm.masked.scatter.v16i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %i…
231 declare void @llvm.masked.scatter.v16i32(<16 x i32> , <16 x i32*> , i32 , <16 x i1> )
379 …%gt1 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %ptr.random, i32 4, <16 x i1> %imask…
380 …%gt2 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %ptr.random, i32 4, <16 x i1> %imask…
1487 …%res = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %ptrs, i32 4, <16 x i1> %mask, <16 x…
[all …]
/external/llvm/test/Analysis/CostModel/X86/
Dmasked-intrinsic-cost.ll69 declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)
72 declare void @llvm.masked.store.v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)
/external/llvm/lib/IR/
DValueTypes.cpp169 case MVT::v16i32: return "v16i32"; in getEVTString()
247 case MVT::v16i32: return VectorType::get(Type::getInt32Ty(Context), 16); in getTypeForEVT()
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td216 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 32, (add SGPR_512)> {
243 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add VGPR_512)> {
DSIISelLowering.cpp64 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass); in SITargetLowering()
71 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); in SITargetLowering()
89 setOperationAction(ISD::LOAD, MVT::v16i32, Custom); in SITargetLowering()
92 setOperationAction(ISD::STORE, MVT::v16i32, Custom); in SITargetLowering()
168 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand); in SITargetLowering()
169 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand); in SITargetLowering()
205 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) { in SITargetLowering()
/external/llvm/test/CodeGen/AMDGPU/
Dctpop.ll9 declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) nounwind readnone
170 %ctpop = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %val) nounwind readnone
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp102 case MVT::v16i32: return "MVT::v16i32"; in getEnumName()

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