/external/llvm/lib/Target/X86/ |
D | X86TargetTransformInfo.cpp | 135 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost() 136 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost() 137 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost() 555 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, in getCastInstrCost() 556 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, in getCastInstrCost() 561 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost() 562 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost() 564 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost() 565 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost() 566 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, in getCastInstrCost() [all …]
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D | X86CallingConv.td | 68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 122 CCIfType<[v16f32, v8f64, v16i32, v8i64], 149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 312 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 332 CCIfType<[v16i32, v8i64, v16f32, v8f64], 372 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>, 415 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 490 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 507 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 526 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], [all …]
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D | X86InstrAVX512.td | 55 // Size of the element type in bits, e.g. 32 for v16i32. 83 !if (!eq (EltSize, 64), "v8i64", "v16i32"), 88 // The corresponding float type, e.g. v16f32 for v16i32 377 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>; 382 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>; 386 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>; 391 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>; 392 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>; 393 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>; 394 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>; [all …]
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D | X86InstrFragmentsSIMD.td | 632 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>; 714 (v16i32 (alignedload512 node:$ptr))>; 799 return (Mgt->getIndex().getValueType() == MVT::v16i32 || 800 Mgt->getBasePtr().getValueType() == MVT::v16i32); 846 return (Sc->getIndex().getValueType() == MVT::v16i32 || 847 Sc->getBasePtr().getValueType() == MVT::v16i32); 867 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
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D | X86ISelLowering.cpp | 1309 addRegisterClass(MVT::v16i32, &X86::VR512RegClass); in X86TargetLowering() 1321 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal); in X86TargetLowering() 1322 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal); in X86TargetLowering() 1323 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal); in X86TargetLowering() 1324 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal); in X86TargetLowering() 1346 setOperationAction(ISD::LOAD, MVT::v16i32, Legal); in X86TargetLowering() 1367 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal); in X86TargetLowering() 1368 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal); in X86TargetLowering() 1371 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal); in X86TargetLowering() 1376 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal); in X86TargetLowering() [all …]
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/external/llvm/include/llvm/CodeGen/ |
D | MachineValueType.h | 91 v16i32 = 42, // 16 x i32 enumerator 259 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 || in is512BitVector() 339 case v16i32: in getVectorElementType() 385 case v16i32: in getVectorNumElements() 492 case v16i32: in getSizeInBits() 621 if (NumElements == 16) return MVT::v16i32; in getVectorVT()
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D | ValueTypes.td | 68 def v16i32 : ValueType<512, 42>; // 16 x i32 vector value
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonIntrinsicsV60.td | 63 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))), 64 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >, 67 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))), 68 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >, 82 def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))), 83 (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1), 102 def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))), 103 (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1), 165 (v16i32 (V6_vandqrt (v512i1 VecPredRegs:$src1), 171 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
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D | HexagonISelLowering.cpp | 197 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_Hexagon_VarArg() 337 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_HexagonVector() 410 LocVT == MVT::v16i32 || LocVT == MVT::v8i64 || in RetCC_Hexagon() 412 LocVT = MVT::v16i32; in RetCC_Hexagon() 413 ValVT = MVT::v16i32; in RetCC_Hexagon() 436 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) { in RetCC_Hexagon() 483 if (LocVT == MVT::v16i32) { in RetCC_HexagonVector() 544 return (ty == MVT::v8i64 || ty == MVT::v16i32 || ty == MVT::v32i16 || in IsHvxVectorType() 888 UseHVX && !UseHVXDbl && (VT == MVT::v16i32 || VT == MVT::v8i64 || in getIndexedAddressParts() 1082 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 || in LowerFormalArguments() [all …]
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D | HexagonInstrInfoV60.td | 816 defm : vS32b_ai_pats <v16i32, v32i32>; 869 defm : vL32b_ai_pats <v16i32, v32i32>; 1001 def : Pat <(v16i32 (selectcc (i32 IntRegs:$lhs), (i32 IntRegs:$rhs), 1002 (v16i32 VectorRegs:$tval), 1003 (v16i32 VectorRegs:$fval), SETEQ)), 1004 (v16i32 (VSelectPseudo_V6 (i32 (C2_cmpeq (i32 IntRegs:$lhs), 1006 (v16i32 VectorRegs:$tval), 1007 (v16i32 VectorRegs:$fval)))>; 1543 def: Pat<(v32i32 (HexagonVCOMBINE (v16i32 VectorRegs:$Vs), 1544 (v16i32 VectorRegs:$Vt))),
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D | HexagonInstrInfoVector.td | 78 defm : bitconvert_vec<v64i8, v16i32>; 79 defm : bitconvert_vec<v8i64 , v16i32>; 80 defm : bitconvert_vec<v32i16, v16i32>;
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D | HexagonISelDAGToDAG.cpp | 405 } else if (LoadedVT == MVT::v16i32 || LoadedVT == MVT::v8i64 || in SelectIndexedLoad() 526 else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 || in SelectIndexedStore() 568 else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 || in SelectIndexedStore()
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/external/llvm/lib/Target/ARM/ |
D | ARMTargetTransformInfo.cpp | 95 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost() 96 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost() 99 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost() 124 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost() 125 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64TargetTransformInfo.cpp | 194 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost() 211 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost() 212 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost() 393 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 }, in getCmpSelInstrCost()
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/external/llvm/test/CodeGen/X86/ |
D | vector-lzcnt-512.ll | 27 %out = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %in, i1 0) 36 %out = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %in, i1 -1) 217 declare <16 x i32> @llvm.ctlz.v16i32(<16 x i32>, i1)
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D | masked_memop.ll | 22 …%res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i3… 35 …%res = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i3… 52 call void @llvm.masked.store.v16i32(<16 x i32>%val, <16 x i32>* %addr, i32 4, <16 x i1>%mask) 328 declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>) 331 declare void @llvm.masked.store.v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)
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D | vector-tzcnt-512.ll | 118 %out = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %in, i1 0) 132 %out = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %in, i1 -1) 269 declare <16 x i32> @llvm.cttz.v16i32(<16 x i32>, i1)
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D | vector-popcnt-512.ll | 104 %out = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %in) 159 declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>)
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D | masked_gather_scatter.ll | 53 declare <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*>, i32, <16 x i1>, <16 x i32>) 131 …%res = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask… 173 …%gt1 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask… 174 …%gt2 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask… 225 …call void @llvm.masked.scatter.v16i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %i… 226 …call void @llvm.masked.scatter.v16i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %i… 231 declare void @llvm.masked.scatter.v16i32(<16 x i32> , <16 x i32*> , i32 , <16 x i1> ) 379 …%gt1 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %ptr.random, i32 4, <16 x i1> %imask… 380 …%gt2 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %ptr.random, i32 4, <16 x i1> %imask… 1487 …%res = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %ptrs, i32 4, <16 x i1> %mask, <16 x… [all …]
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/external/llvm/test/Analysis/CostModel/X86/ |
D | masked-intrinsic-cost.ll | 69 declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>) 72 declare void @llvm.masked.store.v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)
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/external/llvm/lib/IR/ |
D | ValueTypes.cpp | 169 case MVT::v16i32: return "v16i32"; in getEVTString() 247 case MVT::v16i32: return VectorType::get(Type::getInt32Ty(Context), 16); in getTypeForEVT()
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/external/llvm/lib/Target/AMDGPU/ |
D | SIRegisterInfo.td | 216 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 32, (add SGPR_512)> { 243 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add VGPR_512)> {
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D | SIISelLowering.cpp | 64 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass); in SITargetLowering() 71 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); in SITargetLowering() 89 setOperationAction(ISD::LOAD, MVT::v16i32, Custom); in SITargetLowering() 92 setOperationAction(ISD::STORE, MVT::v16i32, Custom); in SITargetLowering() 168 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand); in SITargetLowering() 169 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand); in SITargetLowering() 205 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) { in SITargetLowering()
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/external/llvm/test/CodeGen/AMDGPU/ |
D | ctpop.ll | 9 declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) nounwind readnone 170 %ctpop = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %val) nounwind readnone
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/external/llvm/utils/TableGen/ |
D | CodeGenTarget.cpp | 102 case MVT::v16i32: return "MVT::v16i32"; in getEnumName()
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