/external/llvm/test/CodeGen/AArch64/ |
D | arm64-neon-add-sub.ll | 164 %2 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %1, <1 x double> %c, <1 x double> %a) 171 %1 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %b, <1 x double> %c, <1 x double> %a) 185 %1 = tail call <1 x double> @llvm.aarch64.neon.fabd.v1f64(<1 x double> %a, <1 x double> %b) 192 %1 = tail call <1 x double> @llvm.aarch64.neon.fmax.v1f64(<1 x double> %a, <1 x double> %b) 199 %1 = tail call <1 x double> @llvm.aarch64.neon.fmin.v1f64(<1 x double> %a, <1 x double> %b) 206 %1 = tail call <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double> %a, <1 x double> %b) 213 %1 = tail call <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double> %a, <1 x double> %b) 220 %1 = tail call <1 x double> @llvm.fabs.v1f64(<1 x double> %a) 231 declare <1 x double> @llvm.fabs.v1f64(<1 x double>) 232 declare <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double>, <1 x double>) [all …]
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D | arm64-extract_subvector.ll | 45 define <1 x double> @v1f64(<2 x double> %a) nounwind { 46 ; CHECK-LABEL: v1f64:
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D | vector-fcopysign.ll | 31 ;============ v1f64 42 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %tmp0) 52 %r = call <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b) 56 declare <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b) #0
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D | arm64-neon-simd-shift.ll | 635 %1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double> %a, i32 64) 642 %1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double> %a, i32 64) 649 %1 = tail call <1 x double> @llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64> %a, i32 64) 656 %1 = tail call <1 x double> @llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64> %a, i32 64) 660 declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double>, i32) 661 declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double>, i32) 662 declare <1 x double> @llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64>, i32) 663 declare <1 x double> @llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64>, i32)
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D | arm64-indexed-vector-ldst.ll | 849 %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A) 858 %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A) 864 declare { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double*) 1101 …%ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(d… 1110 …%ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(d… 1116 declare { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(double*) 1353 … double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A) 1362 … double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A) 1368 declare { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f… 1604 %ld1x2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double* %A) [all …]
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D | arm64-ld1.ll | 296 %tmp2 = call %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A) 305 %tmp2 = call %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld3.v1f64.p0f64(double* %A) 314 %tmp2 = call %struct.__neon_float64x1x4_t @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A) 318 declare %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld2.v1f64.p0f64(double*) nounwind readonly 319 declare %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld3.v1f64.p0f64(double*) nounwind readonly 320 declare %struct.__neon_float64x1x4_t @llvm.aarch64.neon.ld4.v1f64.p0f64(double*) nounwind readonly 1049 declare %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double*) nounwind readonly 1089 %val = call %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double* %addr) 1156 declare %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld1x3.v1f64.p0f64(double*) nounwind readonly 1196 %val = call %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld1x3.v1f64.p0f64(double* %addr) [all …]
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D | arm64-st1.ll | 581 declare void @llvm.aarch64.neon.st1x2.v1f64.p0f64(<1 x double>, <1 x double>, double*) nounwind rea… 621 call void @llvm.aarch64.neon.st1x2.v1f64.p0f64(<1 x double> %A, <1 x double> %B, double* %addr) 679 declare void @llvm.aarch64.neon.st1x3.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, double*… 719 …call void @llvm.aarch64.neon.st1x3.v1f64.p0f64(<1 x double> %A, <1 x double> %B, <1 x double> %C, … 778 declare void @llvm.aarch64.neon.st1x4.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, <1 x do… 818 …call void @llvm.aarch64.neon.st1x4.v1f64.p0f64(<1 x double> %A, <1 x double> %B, <1 x double> %C, …
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D | arm64-neon-simd-ldst-one.ll | 256 define <1 x double> @testDUP.v1f64(double* %a, double* %b) #0 { 259 ; CHECK-LABEL: testDUP.v1f64:
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/external/llvm/include/llvm/CodeGen/ |
D | MachineValueType.h | 115 v1f64 = 60, // 1 x f64 enumerator 237 SimpleTy == MVT::v1f64); in is64BitVector() 357 case v1f64: in getVectorElementType() 418 case v1f64: return 1; in getVectorNumElements() 470 case v1f64: return 64; in getSizeInBits() 649 if (NumElements == 1) return MVT::v1f64; in getVectorVT()
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D | ValueTypes.td | 89 def v1f64 : ValueType<64, 60>; // 1 x f64 vector value
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelDAGToDAG.cpp | 2489 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select() 2507 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select() 2525 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select() 2543 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select() 2561 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select() 2579 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select() 2597 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select() 2615 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select() 2633 else if (VT == MVT::v1i64 || VT == MVT::v1f64) in Select() 2648 VT == MVT::v1f64) in Select() [all …]
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D | AArch64InstrInfo.td | 1376 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>; 1519 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), 1680 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), 2001 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>; 2094 def : Pat<(store (v1f64 FPR64:$Rt), 2191 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 2297 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2351 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), 2516 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))), 2544 def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), [all …]
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D | AArch64CallingConvention.td | 70 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 79 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16], 106 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 151 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], 161 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16], 180 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
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D | AArch64ISelLowering.cpp | 96 addDRTypeForNEON(MVT::v1f64); in AArch64TargetLowering() 530 setOperationAction(ISD::FABS, MVT::v1f64, Expand); in AArch64TargetLowering() 531 setOperationAction(ISD::FADD, MVT::v1f64, Expand); in AArch64TargetLowering() 532 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand); in AArch64TargetLowering() 533 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand); in AArch64TargetLowering() 534 setOperationAction(ISD::FCOS, MVT::v1f64, Expand); in AArch64TargetLowering() 535 setOperationAction(ISD::FDIV, MVT::v1f64, Expand); in AArch64TargetLowering() 536 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand); in AArch64TargetLowering() 537 setOperationAction(ISD::FMA, MVT::v1f64, Expand); in AArch64TargetLowering() 538 setOperationAction(ISD::FMUL, MVT::v1f64, Expand); in AArch64TargetLowering() [all …]
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D | AArch64RegisterInfo.td | 396 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
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D | AArch64InstrFormats.td | 5730 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 5747 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), 5904 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
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/external/clang/test/CodeGen/ |
D | systemz-abi-vector.c | 25 typedef __attribute__((vector_size(8))) double v1f64; typedef 118 v1f64 pass_v1f64(v1f64 arg) { return arg; } in pass_v1f64()
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/external/llvm/lib/IR/ |
D | ValueTypes.cpp | 187 case MVT::v1f64: return "v1f64"; in getEVTString() 265 case MVT::v1f64: return VectorType::get(Type::getDoubleTy(Context), 1); in getTypeForEVT()
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/external/llvm/utils/TableGen/ |
D | CodeGenTarget.cpp | 120 case MVT::v1f64: return "MVT::v1f64"; in getEnumName()
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/external/llvm/include/llvm/IR/ |
D | Intrinsics.td | 211 def llvm_v1f64_ty : LLVMType<v1f64>; // 1 x double
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