/external/llvm/test/CodeGen/AMDGPU/ |
D | llvm.SI.sample-masked.ll | 9 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) 22 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) 35 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) 48 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) 61 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) 73 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) 85 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) 92 declare <4 x float> @llvm.SI.sample.v1i32(<1 x i32>, <32 x i8>, <16 x i8>, i32) readnone
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D | llvm.SI.sample.ll | 144 %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) 154 declare <4 x float> @llvm.SI.sample.v1i32(<1 x i32>, <32 x i8>, <16 x i8>, i32) readnone
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/external/llvm/include/llvm/CodeGen/ |
D | MachineValueType.h | 87 v1i32 = 38, // 1 x i32 enumerator 228 SimpleTy == MVT::v1i32 || SimpleTy == MVT::v2f16 || in is32BitVector() 335 case v1i32: in getVectorElementType() 414 case v1i32: in getVectorNumElements() 459 case v1i32: return 32; in getSizeInBits() 617 if (NumElements == 1) return MVT::v1i32; in getVectorVT()
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D | ValueTypes.td | 64 def v1i32 : ValueType<32 , 38>; // 1 x i32 vector value
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/external/clang/test/CodeGen/ |
D | systemz-abi-vector.c | 17 typedef __attribute__((vector_size(4))) int v1i32; typedef 82 v1i32 pass_v1i32(v1i32 arg) { return arg; } in pass_v1i32()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64SchedA57.td | 341 // D form - v1i8, v1i16, v1i32, v1i64 368 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v… 404 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2… 417 // D form - v1i32, v1i64 432 …yc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>; 439 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i6… 470 def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>; 479 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>; 494 // D form - v1i8, v1i16, v1i32, v1i64 508 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>; [all …]
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D | AArch64InstrFormats.td | 5690 def v1i32 : BaseSIMDThreeScalar<U, 0b101, opc, FPR32, asm, []>; 5697 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>; 5702 def v1i32 : BaseSIMDThreeScalar<U, 0b101, opc, FPR32, asm, 5709 def v1i32: BaseSIMDThreeScalarTied<U, 0b10, R, opc, (outs FPR32:$dst), 5919 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,[]>; 5929 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm, 5942 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR32, asm, 5957 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm, 5972 def v1i32 : BaseSIMDTwoScalar<U, 0b10, 0b00, opc, FPR32, FPR64, asm, 7293 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an [all …]
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D | AArch64ISelLowering.cpp | 9887 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32 in getPreferredVectorAction()
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/external/llvm/test/CodeGen/ARM/ |
D | v1-constant-fold.ll | 3 ; PR15611. Check that we don't crash when constant folding v1i32 types.
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D | cttz_vector.ll | 16 declare <1 x i32> @llvm.cttz.v1i32(<1 x i32>, i1) 130 %tmp = call <1 x i32> @llvm.cttz.v1i32(<1 x i32> %a, i1 false) 312 %tmp = call <1 x i32> @llvm.cttz.v1i32(<1 x i32> %a, i1 true)
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/external/llvm/test/CodeGen/AArch64/ |
D | trunc-v1i64.ll | 6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64. 11 ; FIXME: Currently XTN is generated for v1i32, but it can be optimized.
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D | arm64-neon-copy.ll | 872 define <4 x i32> @testDUP.v1i32(<1 x i32> %a) { 873 ; CHECK-LABEL: testDUP.v1i32:
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/external/llvm/lib/IR/ |
D | ValueTypes.cpp | 165 case MVT::v1i32: return "v1i32"; in getEVTString() 243 case MVT::v1i32: return VectorType::get(Type::getInt32Ty(Context), 1); in getTypeForEVT()
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/external/llvm/utils/TableGen/ |
D | CodeGenTarget.cpp | 98 case MVT::v1i32: return "MVT::v1i32"; in getEnumName()
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/external/llvm/include/llvm/IR/ |
D | Intrinsics.td | 186 def llvm_v1i32_ty : LLVMType<v1i32>; // 1 x i32
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonISelLowering.cpp | 1789 MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32, in HexagonTargetLowering()
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