/external/llvm/test/CodeGen/ARM/ |
D | vfloatintrinsics.ll | 255 %v2f64 = type <2 x double> 257 define %v2f64 @test_v2f64.sqrt(%v2f64 %a) { 259 %1 = call %v2f64 @llvm.sqrt.v2f64(%v2f64 %a) 260 ret %v2f64 %1 263 define %v2f64 @test_v2f64.powi(%v2f64 %a, i32 %b) { 265 %1 = call %v2f64 @llvm.powi.v2f64(%v2f64 %a, i32 %b) 266 ret %v2f64 %1 269 define %v2f64 @test_v2f64.sin(%v2f64 %a) { 271 %1 = call %v2f64 @llvm.sin.v2f64(%v2f64 %a) 272 ret %v2f64 %1 [all …]
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-vfloatintrinsics.ll | 253 %v2f64 = type <2 x double> 255 define %v2f64 @test_v2f64.sqrt(%v2f64 %a) { 257 %1 = call %v2f64 @llvm.sqrt.v2f64(%v2f64 %a) 258 ret %v2f64 %1 261 define %v2f64 @test_v2f64.powi(%v2f64 %a, i32 %b) { 263 %1 = call %v2f64 @llvm.powi.v2f64(%v2f64 %a, i32 %b) 264 ret %v2f64 %1 267 define %v2f64 @test_v2f64.sin(%v2f64 %a) { 269 %1 = call %v2f64 @llvm.sin.v2f64(%v2f64 %a) 270 ret %v2f64 %1 [all …]
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D | arm64-vcvt.ll | 26 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> %A) 32 declare <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double>) nounwind readnone 57 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> %A) 63 declare <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double>) nounwind readnone 88 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double> %A) 94 declare <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double>) nounwind readnone 119 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double> %A) 125 declare <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double>) nounwind readnone 150 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> %A) 156 declare <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double>) nounwind readnone [all …]
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D | arm64-fminv.ll | 20 %min = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> %in) 26 declare double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double>) 45 %max = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> %in) 51 declare double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double>) 70 %minnm = call double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double> %in) 76 declare double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double>) 95 %maxnm = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %in) 101 declare double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double>)
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D | arm64-vminmaxnm.ll | 20 …%vmaxnm2.i = tail call <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double> %a, <2 x double> … 41 …%vminnm2.i = tail call <2 x double> @llvm.aarch64.neon.fminnm.v2f64(<2 x double> %a, <2 x double> … 59 declare <2 x double> @llvm.aarch64.neon.fminnm.v2f64(<2 x double>, <2 x double>) nounwind readnone 62 declare <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double>, <2 x double>) nounwind readnone 71 %max = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %in) 78 %min = call double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double> %in) 82 declare double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double>) 83 declare double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double>)
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D | sincospow-vector-expansion.ll | 8 %1 = call <2 x double> @llvm.cos.v2f64(<2 x double> %v1) 17 %1 = call <2 x double> @llvm.sin.v2f64(<2 x double> %v1) 26 %1 = call <2 x double> @llvm.pow.v2f64(<2 x double> %v1, <2 x double> %v2) 31 declare <2 x double> @llvm.cos.v2f64(<2 x double>) 32 declare <2 x double> @llvm.sin.v2f64(<2 x double>) 33 declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>)
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D | arm64-vcvt_n.ll | 35 %vcvt_n1 = tail call <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64> %a, i32 12) 40 %vcvt_n1 = tail call <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64> %a, i32 9) 48 declare <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone 49 declare <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
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/external/llvm/lib/Target/ARM/ |
D | ARMCallingConv.td | 26 // Handle all vector types as either f64 or v2f64. 28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 30 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack 31 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>, 38 CCIfType<[v2f64], CCAssignToStack<16, 4>> 45 // Handle all vector types as either f64 or v2f64. 47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 49 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>, 59 // Handle all vector types as either f64 or v2f64. 61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, [all …]
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D | ARMTargetTransformInfo.cpp | 57 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost() 135 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost() 136 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost() 138 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost() 139 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost() 140 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost() 141 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost() 142 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost() 143 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost() 145 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost() [all …]
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/external/llvm/test/CodeGen/SystemZ/ |
D | vec-round-01.ll | 1 ; Test v2f64 rounding. 11 declare <2 x double> @llvm.rint.v2f64(<2 x double>) 12 declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) 13 declare <2 x double> @llvm.floor.v2f64(<2 x double>) 14 declare <2 x double> @llvm.ceil.v2f64(<2 x double>) 15 declare <2 x double> @llvm.trunc.v2f64(<2 x double>) 16 declare <2 x double> @llvm.round.v2f64(<2 x double>) 22 %res = call <2 x double> @llvm.rint.v2f64(<2 x double> %val) 30 %res = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %val) 38 %res = call <2 x double> @llvm.floor.v2f64(<2 x double> %val) [all …]
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D | vec-log-01.ll | 1 ; Test v2f64 logarithm. 5 declare <2 x double> @llvm.log.v2f64(<2 x double>) 13 %ret = call <2 x double> @llvm.log.v2f64(<2 x double> %val)
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D | vec-mul-02.ll | 5 declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) 40 ; Test a v2f64 multiply-and-add. 46 %ret = call <2 x double> @llvm.fma.v2f64 (<2 x double> %val1, 52 ; Test a v2f64 multiply-and-subtract. 59 %ret = call <2 x double> @llvm.fma.v2f64 (<2 x double> %val1,
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D | vec-abs-05.ll | 1 ; Test f64 and v2f64 absolute. 6 declare <2 x double> @llvm.fabs.v2f64(<2 x double>) 13 %ret = call <2 x double> @llvm.fabs.v2f64(<2 x double> %val) 22 %abs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %val)
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D | vec-sqrt-01.ll | 1 ; Test f64 and v2f64 square root. 6 declare <2 x double> @llvm.sqrt.v2f64(<2 x double>) 12 %ret = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %val)
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrVSX.td | 52 SDTCisVT<0, v2f64>, SDTCisPtrTy<1> 55 SDTCisVT<0, v2f64>, SDTCisPtrTy<1> 105 [(set v2f64:$XT, (int_ppc_vsx_lxvd2x xoaddr:$src))]>; 127 [(store v2f64:$XT, xoaddr:$dst)]>; 150 [(set v2f64:$XT, (fadd v2f64:$XA, v2f64:$XB))]>; 160 [(set v2f64:$XT, (fmul v2f64:$XA, v2f64:$XB))]>; 177 [(set v2f64:$XT, (fsub v2f64:$XA, v2f64:$XB))]>; 253 [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>, 285 [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>, 317 [(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>, [all …]
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/external/llvm/test/CodeGen/Mips/msa/ |
D | basic_operations_float.ll | 9 @v2f64 = global <2 x double> <double 0.0, double 0.0> 53 store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64 56 …volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64 62 …ore volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64 68 store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64 74 store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64 80 store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64 86 store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64 116 store volatile <2 x double> %3, <2 x double>*@v2f64 201 %1 = load <2 x double>, <2 x double>* @v2f64 [all …]
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/external/llvm/test/CodeGen/X86/ |
D | vec_floor.ll | 8 %t = call <2 x double> @llvm.floor.v2f64(<2 x double> %p) 11 declare <2 x double> @llvm.floor.v2f64(<2 x double> %p) 44 %t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p) 47 declare <2 x double> @llvm.ceil.v2f64(<2 x double> %p) 80 %t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p) 83 declare <2 x double> @llvm.trunc.v2f64(<2 x double> %p) 116 %t = call <2 x double> @llvm.rint.v2f64(<2 x double> %p) 119 declare <2 x double> @llvm.rint.v2f64(<2 x double> %p) 152 %t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p) 155 declare <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p) [all …]
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/external/llvm/lib/Target/AArch64/ |
D | AArch64TargetTransformInfo.cpp | 217 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost() 220 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost() 247 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost() 248 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost() 249 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost() 250 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost() 251 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost() 252 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost() 258 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost() 261 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost() [all …]
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D | AArch64CallingConvention.td | 27 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>, 33 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8], 50 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers, 73 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 81 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 87 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>, 93 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8], 109 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 120 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>, 131 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers, [all …]
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/external/llvm/test/Transforms/SLPVectorizer/X86/ |
D | call.ll | 14 ; CHECK: call <2 x double> @llvm.sin.v2f64 35 ; CHECK: call <2 x double> @llvm.cos.v2f64 56 ; CHECK: call <2 x double> @llvm.pow.v2f64 78 ; CHECK: call <2 x double> @llvm.exp2.v2f64 122 ; CHECK: declare <2 x double> @llvm.sin.v2f64(<2 x double>) [[ATTR0:#[0-9]+]] 123 ; CHECK: declare <2 x double> @llvm.cos.v2f64(<2 x double>) [[ATTR0]] 124 ; CHECK: declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) [[ATTR0]] 125 ; CHECK: declare <2 x double> @llvm.exp2.v2f64(<2 x double>) [[ATTR0]]
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/external/llvm/test/CodeGen/PowerPC/ |
D | vec_rounding.ll | 9 declare <2 x double> @llvm.floor.v2f64(<2 x double> %p) 12 %t = call <2 x double> @llvm.floor.v2f64(<2 x double> %p) 31 declare <2 x double> @llvm.ceil.v2f64(<2 x double> %p) 34 %t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p) 53 declare <2 x double> @llvm.trunc.v2f64(<2 x double> %p) 56 %t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p) 75 declare <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p) 78 %t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p)
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D | vsx-fma-m.ll | 179 %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a) 181 %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a) 206 %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a) 208 %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a) 211 %2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a) 244 %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a) 246 %1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a) 247 %2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %1) 250 %3 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a) 302 %0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a) [all …]
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/external/llvm/test/Transforms/BBVectorize/ |
D | simple-int.ll | 39 ; CHECK: %Y1 = call <2 x double> @llvm.fma.v2f64(<2 x double> %X1, <2 x double> %X1.v.i0.2, <2 x do… 65 ; CHECK: %Y1 = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %X1, <2 x double> %X1.v.i0.2, <2 … 89 ; CHECK: %Y1 = call <2 x double> @llvm.cos.v2f64(<2 x double> %X1) 114 ; CHECK: %Y1 = call <2 x double> @llvm.powi.v2f64(<2 x double> %X1, i32 %P) 155 ; CHECK: %Y1 = call <2 x double> @llvm.round.v2f64(<2 x double> %X1) 181 ; CHECK: %Y1 = call <2 x double> @llvm.copysign.v2f64(<2 x double> %X1, <2 x double> %Y1.v.i1.2) 206 ; CHECK: %Y1 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %X1) 231 ; CHECK: %Y1 = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %X1) 256 ; CHECK: %Y1 = call <2 x double> @llvm.rint.v2f64(<2 x double> %X1) 281 ; CHECK: %Y1 = call <2 x double> @llvm.trunc.v2f64(<2 x double> %X1) [all …]
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | AMDILISelLowering.cpp | 65 (int)MVT::v2f64, in InitAMDILLowering() 93 (int)MVT::v2f64, in InitAMDILLowering() 189 setOperationAction(ISD::FADD, MVT::v2f64, Expand); in InitAMDILLowering() 190 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); in InitAMDILLowering() 191 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); in InitAMDILLowering() 192 setOperationAction(ISD::FP_ROUND_INREG, MVT::v2f64, Expand); in InitAMDILLowering() 193 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand); in InitAMDILLowering() 197 setOperationAction(ISD::TRUNCATE, MVT::v2f64, Expand); in InitAMDILLowering() 198 setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand); in InitAMDILLowering() 199 setOperationAction(ISD::ZERO_EXTEND, MVT::v2f64, Expand); in InitAMDILLowering() [all …]
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZInstrVector.td | 128 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)), 145 def : Pat<(v2f64 (z_vllezf64 bdxaddr12only:$addr)), 155 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index), 180 defm : ReplicatePeephole<VLREPG, v2f64, load, f64>; 204 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr, 231 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>; 239 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>; 254 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16:$index)), 338 defm : GenericVectorOps<v2f64, v2i64>; 848 def : Pat<(v4f32 (z_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>; [all …]
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