| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 59 v2i1 = 13, // 2 x i1 enumerator
104 FIRST_INTEGER_VECTOR_VALUETYPE = v2i1,
123 FIRST_VECTOR_VALUETYPE = v2i1,
310 case v2i1: in getVectorElementType()
404 case v2i1: in getVectorNumElements()
442 case v2i1: return 2; in getSizeInBits()
586 if (NumElements == 2) return MVT::v2i1; in getVectorVT()
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| D | ValueTypes.td | 36 def v2i1 : ValueType<2 , 13>; // 2 x i1 vector value
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoVector.td | 14 def V2I1: PatLeaf<(v2i1 PredRegs:$R)>;
276 def: vcmp_vi1_pat<A2_vcmpweq, seteq, V2I32, v2i1>;
277 def: vcmp_vi1_pat<A2_vcmpwgt, setgt, V2I32, v2i1>;
278 def: vcmp_vi1_pat<A2_vcmpwgtu, setugt, V2I32, v2i1>;
360 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, v2i1>;
367 def: InvertCmp_pat<A2_vcmpwgtu, setult, V2I32, v2i1>;
371 def: Pat<(v2i1 (setne V2I32:$Rs, V2I32:$Rt)),
372 (C2_not (v2i1 (A2_vcmpbeq V2I32:$Rs, V2I32:$Rt)))>;
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| D | HexagonRegisterInfo.td | 239 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32,
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| D | HexagonISelLowering.cpp | 1233 SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp); in LowerSETCC()
1548 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa in HexagonTargetLowering()
1788 for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1, in HexagonTargetLowering()
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 140 case MVT::v2i1: return "v2i1"; in getEVTString()
218 case MVT::v2i1: return VectorType::get(Type::getInt1Ty(Context), 2); in getTypeForEVT()
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | vec-move-16.ll | 63 ; Test a v2i1->v2i64 extension.
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| D | vec-move-15.ll | 63 ; Test a v2i1->v2i64 extension.
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| D | vec-and-03.ll | 71 ; Test a v2i1->v2i64 extension.
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| D | vec-move-17.ll | 63 ; Test a v2i64->v2i1 truncation.
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| D | vec-shift-07.ll | 71 ; Test a v2i1->v2i64 extension.
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| /external/llvm/lib/Target/X86/ |
| D | X86CallingConv.td | 46 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
289 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
562 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
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| D | X86RegisterInfo.td | 481 def VK2 : RegisterClass<"X86", [v2i1], 8, (add VK1)> {let Size = 8;}
489 def VK2WM : RegisterClass<"X86", [v2i1], 8, (sub VK2, K0)> {let Size = 8;}
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| D | X86InstrAVX512.td | 2186 def : Pat<(v2i1 (scalar_to_vector VK1:$src)),
2272 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2373 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2477 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2506 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2507 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2509 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2514 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
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| D | X86ISelLowering.cpp | 1413 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom); in X86TargetLowering()
1704 addRegisterClass(MVT::v2i1, &X86::VK2RegClass); in X86TargetLowering()
1707 setOperationAction(ISD::SETCC, MVT::v2i1, Custom); in X86TargetLowering()
1713 setOperationAction(ISD::SELECT, MVT::v2i1, Custom); in X86TargetLowering()
1715 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom); in X86TargetLowering()
1716 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom); in X86TargetLowering()
1893 case 2: return MVT::v2i1; in getSetCCResultType()
11193 case MVT::v2i1: in lower1BitVectorShuffle()
14897 if (VT == MVT::v4i1 || VT == MVT::v2i1) { in LowerSELECT()
19839 assert((MaskVT == MVT::v2i1 || MaskVT == MVT::v2i64) && in LowerMSCATTER()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 73 case MVT::v2i1: return "MVT::v2i1"; in getEnumName()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 158 def llvm_v2i1_ty : LLVMType<v2i1>; // 2 x i1
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 106 setOperationAction(ISD::SETCC, MVT::v2i1, Expand); in SITargetLowering()
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom); in SITargetLowering()
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| D | R600ISelLowering.cpp | 106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
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| D | AMDGPUISelLowering.cpp | 146 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand); in AMDGPUTargetLowering()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 61 case MVT::v2i1: in IsPTXVectorType()
|