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Searched refs:v32i16 (Results 1 – 20 of 20) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h83 v32i16 = 35, // 32 x i16 enumerator
259 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 || in is512BitVector()
332 case v32i16: in getVectorElementType()
379 case v32i16: in getVectorNumElements()
491 case v32i16: in getSizeInBits()
612 if (NumElements == 32) return MVT::v32i16; in getVectorVT()
DValueTypes.td60 def v32i16 : ValueType<512, 35>; // 32 x i16 vector value
/external/llvm/test/CodeGen/X86/
Dvector-lzcnt-512.ll68 %out = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %in, i1 0)
100 %out = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %in, i1 -1)
218 declare <32 x i16> @llvm.ctlz.v32i16(<32 x i16>, i1)
Dvector-tzcnt-512.ll168 %out = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %in, i1 0)
204 %out = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %in, i1 -1)
270 declare <32 x i16> @llvm.cttz.v32i16(<32 x i16>, i1)
Dvector-popcnt-512.ll132 %out = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %in)
160 declare <32 x i16> @llvm.ctpop.v32i16(<32 x i16>)
/external/llvm/lib/Target/X86/
DX86CallingConv.td68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
312 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
415 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
490 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
507 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
526 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
620 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
626 v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
DX86InstrAVX512.td378 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
383 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
387 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
393 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
396 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
397 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
398 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
399 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
400 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
401 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
[all …]
DX86ISelLowering.cpp1325 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal); in X86TargetLowering()
1326 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal); in X86TargetLowering()
1612 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) { in X86TargetLowering()
1619 addRegisterClass(MVT::v32i16, &X86::VR512RegClass); in X86TargetLowering()
1625 setOperationAction(ISD::LOAD, MVT::v32i16, Legal); in X86TargetLowering()
1629 setOperationAction(ISD::ADD, MVT::v32i16, Legal); in X86TargetLowering()
1631 setOperationAction(ISD::SUB, MVT::v32i16, Legal); in X86TargetLowering()
1633 setOperationAction(ISD::MUL, MVT::v32i16, Legal); in X86TargetLowering()
1634 setOperationAction(ISD::MULHS, MVT::v32i16, Legal); in X86TargetLowering()
1635 setOperationAction(ISD::MULHU, MVT::v32i16, Legal); in X86TargetLowering()
[all …]
DX86RegisterInfo.td465 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
DX86InstrFragmentsSIMD.td631 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
/external/llvm/lib/IR/
DValueTypes.cpp162 case MVT::v32i16: return "v32i16"; in getEVTString()
240 case MVT::v32i16: return VectorType::get(Type::getInt16Ty(Context), 32); in getTypeForEVT()
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td87 def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
88 (v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1),
107 def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))),
108 (v32i16 (V6_vandqrt(v512i1 VecPredRegs:$src1),
DHexagonISelLowering.cpp197 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_Hexagon_VarArg()
337 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_HexagonVector()
409 } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 || in RetCC_Hexagon()
544 return (ty == MVT::v8i64 || ty == MVT::v16i32 || ty == MVT::v32i16 || in IsHvxVectorType()
889 VT == MVT::v32i16 || VT == MVT::v64i8); in getIndexedAddressParts()
1083 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { in LowerFormalArguments()
1567 addRegisterClass(MVT::v32i16, &Hexagon::VectorRegsRegClass); in HexagonTargetLowering()
2670 case MVT::v32i16: in getRegForInlineAsmConstraint()
2681 case MVT::v32i16: in getRegForInlineAsmConstraint()
2827 case MVT::v32i16: in findRepresentativeClass()
DHexagonISelDAGToDAG.cpp406 LoadedVT == MVT::v32i16 || LoadedVT == MVT::v64i8) { in SelectIndexedLoad()
527 StoredVT == MVT::v32i16 || StoredVT == MVT::v64i8) { in SelectIndexedStore()
569 StoredVT == MVT::v32i16 || StoredVT == MVT::v64i8) in SelectIndexedStore()
DHexagonRegisterInfo.td217 def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512,
DHexagonInstrInfoVector.td80 defm : bitconvert_vec<v32i16, v16i32>;
DHexagonInstrInfoV60.td815 defm : vS32b_ai_pats <v32i16, v64i16>;
868 defm : vL32b_ai_pats <v32i16, v64i16>;
DHexagonInstrInfo.cpp2285 VT == MVT::v32i16 || VT == MVT::v64i8) { in isValidAutoIncImm()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp95 case MVT::v32i16: return "MVT::v32i16"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td182 def llvm_v32i16_ty : LLVMType<v32i16>; // 32 x i16