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Searched refs:v32i8 (Results 1 – 24 of 24) sorted by relevance

/external/clang/test/CodeGen/
Dsystemz-abi-vector.c36 typedef __attribute__((vector_size(32))) char v32i8; typedef
62 v32i8 pass_v32i8(v32i8 arg) { return arg; } in pass_v32i8()
158 struct agg_v32i8 { v32i8 a; };
349 v32i8 va_v32i8(__builtin_va_list l) { return __builtin_va_arg(l, v32i8); } in va_v32i8()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h73 v32i8 = 26, // 32 x i8 enumerator
251 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || in is256BitVector()
323 case v32i8: in getVectorElementType()
378 case v32i8: in getVectorNumElements()
483 case v32i8: in getSizeInBits()
601 if (NumElements == 32) return MVT::v32i8; in getVectorVT()
DValueTypes.td50 def v32i8 : ValueType<256, 26>; // 32 x i8 vector value
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp191 { ISD::SHL, MVT::v32i8, 2 }, in getArithmeticInstrCost()
192 { ISD::SRL, MVT::v32i8, 4 }, in getArithmeticInstrCost()
193 { ISD::SRA, MVT::v32i8, 4 }, in getArithmeticInstrCost()
212 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. in getArithmeticInstrCost()
215 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. in getArithmeticInstrCost()
218 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. in getArithmeticInstrCost()
224 { ISD::SDIV, MVT::v32i8, 32*20 }, in getArithmeticInstrCost()
228 { ISD::UDIV, MVT::v32i8, 32*20 }, in getArithmeticInstrCost()
247 { ISD::SHL, MVT::v32i8, 2 }, // psllw. in getArithmeticInstrCost()
256 { ISD::SRL, MVT::v32i8, 2 }, // psrlw. in getArithmeticInstrCost()
[all …]
DX86CallingConv.td50 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
293 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
306 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
328 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
369 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
411 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
486 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
502 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86InstrSSE.td352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
353 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
369 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
[all …]
DX86ISelLowering.cpp1058 setOperationAction(ISD::ROTL, MVT::v32i8, Custom); in X86TargetLowering()
1065 addRegisterClass(MVT::v32i8, &X86::VR256RegClass); in X86TargetLowering()
1119 setOperationAction(ISD::SRL, MVT::v32i8, Custom); in X86TargetLowering()
1122 setOperationAction(ISD::SHL, MVT::v32i8, Custom); in X86TargetLowering()
1125 setOperationAction(ISD::SRA, MVT::v32i8, Custom); in X86TargetLowering()
1127 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); in X86TargetLowering()
1149 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom); in X86TargetLowering()
1154 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom); in X86TargetLowering()
1158 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom); in X86TargetLowering()
1176 setOperationAction(ISD::ADD, MVT::v32i8, Legal); in X86TargetLowering()
[all …]
DX86RegisterInfo.td451 def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
476 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
DX86InstrAVX512.td445 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
449 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
454 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
456 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
457 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
458 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
459 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
460 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
461 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
470 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
[all …]
DX86InstrFragmentsSIMD.td860 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
/external/llvm/test/CodeGen/X86/
Davx2-cmp.ll25 define <32 x i8> @v32i8-cmp(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
53 define <32 x i8> @v32i8-cmpeq(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
Davx-cmp.ll83 define <32 x i8> @v32i8-cmp(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
127 define <32 x i8> @v32i8-cmpeq(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
Dvector-popcnt-256.ll176 %out = call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %in)
212 …%out = call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> <i8 256, i8 -1, i8 0, i8 255, i8 -65536, i8 7, i…
219 declare <32 x i8> @llvm.ctpop.v32i8(<32 x i8>)
Davx2-arith.ll80 ; CHECK: mul-v32i8
101 define <32 x i8> @mul-v32i8(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
Dvector-tzcnt-256.ll402 %out = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> %in, i1 0)
451 %out = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> %in, i1 -1)
514 …%out = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> <i8 256, i8 -1, i8 0, i8 255, i8 -65536, i8 7, i8…
523 …%out = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> <i8 256, i8 -1, i8 0, i8 255, i8 -65536, i8 7, i8…
530 declare <32 x i8> @llvm.cttz.v32i8(<32 x i8>, i1)
Dvector-lzcnt-256.ll1061 %out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %in, i1 0)
1363 %out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %in, i1 -1)
1496 …%out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> <i8 256, i8 -1, i8 0, i8 255, i8 -65536, i8 7, i8…
1515 …%out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> <i8 256, i8 -1, i8 0, i8 255, i8 -65536, i8 7, i8…
1522 declare <32 x i8> @llvm.ctlz.v32i8(<32 x i8>, i1)
/external/llvm/lib/IR/
DValueTypes.cpp153 case MVT::v32i8: return "v32i8"; in getEVTString()
231 case MVT::v32i8: return VectorType::get(Type::getInt8Ty(Context), 32); in getTypeForEVT()
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td211 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 32, (add SGPR_256)> {
239 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 32, (add VGPR_256)> {
DSIInstructions.td2116 defm : SMRD_Pattern <"S_LOAD_DWORDX8", v32i8>;
2351 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2356 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2361 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
2366 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
2372 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
2378 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
2431 (name addr_type:$addr, v32i8:$rsrc, imm),
2436 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
2441 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
[all …]
DSIISelLowering.cpp45 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); in SITargetLowering()
DSIInstrInfo.td126 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp86 case MVT::v32i8: return "MVT::v32i8"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td172 def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp192 LocVT == MVT::v32i8) { in CC_Hexagon_VarArg()
257 if (LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || LocVT == MVT::v32i8) { in CC_Hexagon()