/external/llvm/test/CodeGen/PowerPC/ |
D | vaddsplat.ll | 8 %v4i32 = type <4 x i32> 12 define void @test_v4i32_pos_even(%v4i32* %P, %v4i32* %S) { 13 %p = load %v4i32, %v4i32* %P 14 %r = add %v4i32 %p, < i32 18, i32 18, i32 18, i32 18 > 15 store %v4i32 %r, %v4i32* %S 23 define void @test_v4i32_neg_even(%v4i32* %P, %v4i32* %S) { 24 %p = load %v4i32, %v4i32* %P 25 %r = add %v4i32 %p, < i32 -28, i32 -28, i32 -28, i32 -28 > 26 store %v4i32 %r, %v4i32* %S 78 define void @test_v4i32_pos_odd(%v4i32* %P, %v4i32* %S) { [all …]
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrAltivec.td | 407 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 418 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 421 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 424 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 445 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 448 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 451 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 475 v4i32, v4i32, v16i8>; 476 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 498 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; [all …]
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/external/libvpx/libvpx/vp8/common/mips/msa/ |
D | vp8_macros_msa.h | 29 #define LD_SW(...) LD_W(v4i32, __VA_ARGS__) 40 #define ST_SW(...) ST_W(v4i32, __VA_ARGS__) 452 out0_m = __msa_copy_u_w((v4i32)in0, idx0); \ 453 out1_m = __msa_copy_u_w((v4i32)in0, idx1); \ 454 out2_m = __msa_copy_u_w((v4i32)in1, idx2); \ 455 out3_m = __msa_copy_u_w((v4i32)in1, idx3); \ 673 #define DOTP_SH4_SW(...) DOTP_SH4(v4i32, __VA_ARGS__) 687 out0 = (RTYPE)__msa_dotp_s_d((v4i32)mult0, (v4i32)cnst0); \ 688 out1 = (RTYPE)__msa_dotp_s_d((v4i32)mult1, (v4i32)cnst1); \ 729 out0 = (RTYPE)__msa_dpadd_s_w((v4i32)out0, (v8i16)mult0, (v8i16)cnst0); \ [all …]
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/external/llvm/test/Transforms/InstCombine/ |
D | 2012-04-23-Neon-Intrinsics.ll | 5 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) noun… 13 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1,… 22 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x … 30 …%b = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <… 38 …%b = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <… 46 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x … 50 ; CHECK-NEXT: %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, … 56 …%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x … 64 declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone 65 declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone [all …]
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/external/llvm/test/Analysis/CostModel/X86/ |
D | scalarize.ll | 13 declare %i4 @llvm.bswap.v4i32(%i4) 16 declare %i4 @llvm.ctpop.v4i32(%i4) 24 ; CHECK32: cost of 12 {{.*}}bswap.v4i32 25 ; CHECK64: cost of 12 {{.*}}bswap.v4i32 26 %r2 = call %i4 @llvm.bswap.v4i32(%i4 undef) 31 ; CHECK32: cost of 12 {{.*}}ctpop.v4i32 32 ; CHECK64: cost of 12 {{.*}}ctpop.v4i32 33 %r4 = call %i4 @llvm.ctpop.v4i32(%i4 undef)
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/external/clang/test/CodeGen/ |
D | mips-vector-arg.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef 24 extern test_v4i32_2(v4i32, int, v4i32); 25 void test_v4i32(v4i32 a1, int a2, v4i32 a3) { in test_v4i32()
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D | mips-vector-return.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef 28 v4i32 test_v4i32(int a) { in test_v4i32() 29 return (v4i32){0, a, 0, 0}; in test_v4i32()
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D | compound-literal.c | 6 typedef int v4i32 __attribute((vector_size(16))); 7 v4i32 *y = &(v4i32){1,2,3,4};
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D | mips-varargs.c | 10 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef 130 v4i32 v = va_arg(va, v4i32); in test_v4i32()
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/external/llvm/test/CodeGen/AMDGPU/ |
D | llvm.SI.image.sample.o.ll | 9 …%r = call <4 x float> @llvm.SI.image.sample.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> un… 23 …%r = call <4 x float> @llvm.SI.image.sample.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32>… 37 …%r = call <4 x float> @llvm.SI.image.sample.d.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> … 51 …%r = call <4 x float> @llvm.SI.image.sample.d.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i3… 65 …%r = call <4 x float> @llvm.SI.image.sample.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> … 79 …%r = call <4 x float> @llvm.SI.image.sample.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> … 93 …%r = call <4 x float> @llvm.SI.image.sample.b.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i3… 107 …%r = call <4 x float> @llvm.SI.image.sample.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32>… 121 …%r = call <4 x float> @llvm.SI.image.sample.cd.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32>… 135 …%r = call <4 x float> @llvm.SI.image.sample.cd.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i… [all …]
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D | llvm.SI.image.sample.ll | 9 …%r = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> unde… 23 …%r = call <4 x float> @llvm.SI.image.sample.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> u… 37 …%r = call <4 x float> @llvm.SI.image.sample.d.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> un… 51 …%r = call <4 x float> @llvm.SI.image.sample.d.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32>… 65 …%r = call <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> un… 79 …%r = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> un… 93 …%r = call <4 x float> @llvm.SI.image.sample.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32>… 107 …%r = call <4 x float> @llvm.SI.image.sample.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> u… 121 …%r = call <4 x float> @llvm.SI.image.sample.cd.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> u… 135 …%r = call <4 x float> @llvm.SI.image.sample.cd.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32… [all …]
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D | llvm.SI.gather4.ll | 21 …%r = call <4 x float> @llvm.SI.gather4.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i3… 34 …%r = call <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef,… 47 …%r = call <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, … 60 …%r = call <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, … 73 …%r = call <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> unde… 112 …%r = call <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef,… 127 …%r = call <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, … 140 …%r = call <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> unde… 166 …%r = call <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef… 192 …%r = call <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef… [all …]
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/external/libvpx/libvpx/vpx_dsp/mips/ |
D | macros_msa.h | 28 #define LD_SW(...) LD_W(v4i32, __VA_ARGS__) 38 #define ST_SW(...) ST_W(v4i32, __VA_ARGS__) 489 out0_m = __msa_copy_u_w((v4i32)in, 0); \ 490 out1_m = __msa_copy_u_w((v4i32)in, 1); \ 511 out0_m = __msa_copy_u_w((v4i32)in0, idx0); \ 512 out1_m = __msa_copy_u_w((v4i32)in0, idx1); \ 513 out2_m = __msa_copy_u_w((v4i32)in1, idx2); \ 514 out3_m = __msa_copy_u_w((v4i32)in1, idx3); \ 612 #define SLDI_B2_0_SW(...) SLDI_B2_0(v4i32, __VA_ARGS__) 727 #define DOTP_SH2_SW(...) DOTP_SH2(v4i32, __VA_ARGS__) [all …]
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D | txfm_macros_msa.h | 18 v4i32 s0_m, s1_m, s2_m, s3_m; \ 20 s0_m = (v4i32)__msa_fill_h(cnst1); \ 36 v4i32 tp0_m, tp1_m, tp2_m, tp3_m, tp4_m; \ 37 v4i32 tp5_m, tp6_m, tp7_m, tp8_m, tp9_m; \ 53 v4i32 tp0_m, tp1_m; \ 63 v4i32 madd0_m, madd1_m, madd2_m, madd3_m; \ 76 v4i32 tmp0_m, tmp1_m, tmp2_m, tmp3_m, m4_m, m5_m; \
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D | intrapred_msa.c | 167 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 3); in intra_predict_dc_4x4_msa() 169 val0 = __msa_copy_u_w((v4i32)store, 0); in intra_predict_dc_4x4_msa() 182 data = (v16i8)__msa_insert_w((v4i32)data, 0, val0); in intra_predict_dc_tl_4x4_msa() 185 sum_w = (v4u32)__msa_srari_w((v4i32)sum_w, 2); in intra_predict_dc_tl_4x4_msa() 187 val0 = __msa_copy_u_w((v4i32)store, 0); in intra_predict_dc_tl_4x4_msa() 196 out = __msa_copy_u_w((v4i32)store, 0); in intra_predict_128dc_4x4_msa() 217 sum_w = (v4u32)__msa_pckev_w((v4i32)sum_d, (v4i32)sum_d); in intra_predict_dc_8x8_msa() 219 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 4); in intra_predict_dc_8x8_msa() 242 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 3); in intra_predict_dc_tl_8x8_msa() 276 sum_w = (v4u32)__msa_pckev_w((v4i32)sum_d, (v4i32)sum_d); in intra_predict_dc_16x16_msa() [all …]
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D | fwd_txfm_msa.h | 19 v4i32 vec_w_m; \ 35 v4i32 vec4_m, vec5_m, vec6_m, vec7_m; \ 308 v4i32 temp_m; \ 309 v4i32 one_m = __msa_ldi_w(1); \ 339 v4i32 s0_m, s1_m, s2_m, s3_m, s4_m, s5_m, s6_m, s7_m; \ 341 v4i32 k0_m = __msa_fill_w((int32_t) const0); \ 357 out0 = __msa_pckev_w((v4i32)tp0_m, (v4i32)tp1_m); \ 358 out1 = __msa_pckev_w((v4i32)tp2_m, (v4i32)tp3_m); \ 366 out2 = __msa_pckev_w((v4i32)tp0_m, (v4i32)tp1_m); \ 367 out3 = __msa_pckev_w((v4i32)tp2_m, (v4i32)tp3_m); \
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/external/libvpx/libvpx/vp8/encoder/mips/msa/ |
D | dct_msa.c | 48 v4i32 tmp0_m; \ 49 v4i32 one_m = __msa_ldi_w(1); \ 60 v4i32 tmp0_m; \ 62 v4i32 one_m = __msa_ldi_w(1); \ 75 v4i32 out0, out1, out2, out3; in vp8_short_fdct4x4_msa() 88 out0 = (v4i32)__msa_ilvev_h(zero, in1); in vp8_short_fdct4x4_msa() 90 out1 = __msa_splati_w((v4i32)coeff, 0); in vp8_short_fdct4x4_msa() 107 out1 = __msa_splati_w((v4i32)coeff, 1); in vp8_short_fdct4x4_msa() 111 out1 += (v4i32)temp1; in vp8_short_fdct4x4_msa() 123 v4i32 vec0_w, vec1_w, vec2_w, vec3_w; in vp8_short_fdct8x4_msa() [all …]
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D | encodeopt_msa.c | 20 v4i32 diff0, diff1; in vp8_block_error_msa() 52 v4i32 diff0, diff1; in vp8_mbblock_error_msa() 59 mask0 = (v16u8)__msa_insve_w((v4i32)mask0, 0, (v4i32)zero); in vp8_mbblock_error_msa() 86 diff0 = (v4i32)__msa_bmnz_v(zero, (v16u8)diff0, mask0); in vp8_mbblock_error_msa() 98 diff0 = (v4i32)__msa_bmnz_v(zero, (v16u8)diff0, mask0); in vp8_mbblock_error_msa() 121 v4i32 diff0, diff1; in vp8_mbuverror_msa()
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/external/llvm/lib/Target/X86/ |
D | X86TargetTransformInfo.cpp | 151 { ISD::SHL, MVT::v4i32, 1 }, in getArithmeticInstrCost() 152 { ISD::SRL, MVT::v4i32, 1 }, in getArithmeticInstrCost() 153 { ISD::SRA, MVT::v4i32, 1 }, in getArithmeticInstrCost() 184 { ISD::SHL, MVT::v4i32, 1 }, in getArithmeticInstrCost() 185 { ISD::SRL, MVT::v4i32, 2 }, in getArithmeticInstrCost() 186 { ISD::SRA, MVT::v4i32, 2 }, in getArithmeticInstrCost() 250 { ISD::SHL, MVT::v4i32, 1 }, // pslld in getArithmeticInstrCost() 259 { ISD::SRL, MVT::v4i32, 1 }, // psrld. in getArithmeticInstrCost() 268 { ISD::SRA, MVT::v4i32, 1 }, // psrad. in getArithmeticInstrCost() 275 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence in getArithmeticInstrCost() [all …]
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/external/llvm/test/CodeGen/ARM/ |
D | vcvt-v8.ll | 6 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %tmp1) 22 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %tmp1) 38 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %tmp1) 54 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %tmp1) 70 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %tmp1) 86 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %tmp1) 102 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %tmp1) 118 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float> %tmp1) 130 declare <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float>) nounwind readnone 132 declare <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float>) nounwind readnone [all …]
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/external/llvm/test/Transforms/EarlyCSE/AArch64/ |
D | intrinsics.ll | 8 ; CHECK-NOT: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8 25 call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %4, i8* %0) 27 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %5) 42 ; CHECK-NOT: call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %3, i8* %0) 43 ; CHECK: call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %4, i8* %0) 60 call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %3, i8* %0) 61 call void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %3, <4 x i32> %4, i8* %0) 63 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %5) 78 ; CHECK: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8 79 ; CHECK-NOT: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8 [all …]
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/external/llvm/lib/Target/AMDGPU/ |
D | SITypeRewriter.cpp | 39 Type *v4i32; member in __anon0ad1b8870111::SITypeRewriter 60 v4i32 = VectorType::get(Type::getInt32Ty(M.getContext()), 4); in doInitialization() 81 PointerType::get(v4i32,PtrTy->getPointerAddressSpace())); in visitLoadInst() 105 Args.push_back(Builder.CreateBitCast(Arg, v4i32)); in visitCallInst() 106 Types.push_back(v4i32); in visitCallInst() 141 if (I.getDestTy() != v4i32) { in visitBitCast() 146 if (Op->getSrcTy() == v4i32) { in visitBitCast()
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-neon-copyPhysReg-tuple.ll | 10 …%vld = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32> <i32 -1… 12 …%vld1 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32> %extra… 24 …%vld = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i… 26 …%vld1 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x … 39 …%vld = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p… 41 …%vld1 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.… 46 declare { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32>, <4 x i32>, i64, … 47 declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i32>, <4 x … 48 declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x …
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D | arm64-AnInfiniteLoopInDAGCombine.ll | 5 ; (1) Replacing.3 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4] 6 ; With: 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4] 8 ; (2) Replacing.2 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4] 9 ; With: 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4]
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/external/libvpx/libvpx/vp9/encoder/mips/msa/ |
D | vp9_avg_msa.c | 30 sum = (v4u32)__msa_srari_w((v4i32)sum, 6); in vp9_avg_8x8_msa() 31 sum_out = __msa_copy_u_w((v4i32)sum, 0); in vp9_avg_8x8_msa() 52 sum1 = (v4u32)__msa_srari_w((v4i32)sum2, 4); in vp9_avg_4x4_msa() 53 sum_out = __msa_copy_u_w((v4i32)sum1, 0); in vp9_avg_4x4_msa()
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