| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 61 v8i1 = 15, // 8 x i1 enumerator
312 case v8i1: in getVectorElementType()
388 case v8i1: in getVectorNumElements()
446 case v8i1: return 8; in getSizeInBits()
588 if (NumElements == 8) return MVT::v8i1; in getVectorVT()
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| D | ValueTypes.td | 38 def v8i1 : ValueType<8 , 15>; // 8 x i1 vector value
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| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 577 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, in getCastInstrCost()
588 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, in getCastInstrCost()
613 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, in getCastInstrCost()
614 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, in getCastInstrCost()
644 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, in getCastInstrCost()
645 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, in getCastInstrCost()
667 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, in getCastInstrCost()
680 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, in getCastInstrCost()
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| D | X86InstrAVX512.td | 1401 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1408 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1620 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1625 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1883 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1888 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1893 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
2056 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
2081 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2083 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
[all …]
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| D | X86CallingConv.td | 48 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
291 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
564 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
735 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>,
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| D | X86RegisterInfo.td | 483 def VK8 : RegisterClass<"X86", [v8i1], 8, (add VK4)> {let Size = 8;}
491 def VK8WM : RegisterClass<"X86", [v8i1], 8, (sub VK8, K0)> {let Size = 8;}
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| D | X86ISelLowering.cpp | 1315 addRegisterClass(MVT::v8i1, &X86::VK8RegClass); in X86TargetLowering()
1372 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom); in X86TargetLowering()
1410 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom); in X86TargetLowering()
1441 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom); in X86TargetLowering()
1475 setOperationAction(ISD::SETCC, MVT::v8i1, Custom); in X86TargetLowering()
1479 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom); in X86TargetLowering()
1483 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom); in X86TargetLowering()
1484 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom); in X86TargetLowering()
1490 setOperationAction(ISD::SELECT, MVT::v8i1, Custom); in X86TargetLowering()
1709 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom); in X86TargetLowering()
[all …]
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| D | X86InstrCompiler.td | 552 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>;
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 142 case MVT::v8i1: return "v8i1"; in getEVTString()
220 case MVT::v8i1: return VectorType::get(Type::getInt1Ty(Context), 8); in getTypeForEVT()
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | vec-move-16.ll | 13 ; Test a v8i1->v8i16 extension.
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| D | vec-move-15.ll | 13 ; Test a v8i1->v8i16 extension.
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| D | vec-and-03.ll | 16 ; Test a v8i1->v8i16 extension.
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| D | vec-move-17.ll | 13 ; Test a v8i16->v8i1 truncation.
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| D | vec-shift-07.ll | 16 ; Test a v8i1->v8i16 extension.
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 392 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 }, in getCmpSelInstrCost()
395 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost }, in getCmpSelInstrCost()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoVector.td | 16 def V8I1: PatLeaf<(v8i1 PredRegs:$R)>;
356 def: InvertCmp_pat<A4_vcmpbgt, setlt, V8I8, v8i1>;
363 def: InvertCmp_pat<A2_vcmpbgtu, setult, V8I8, v8i1>;
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| D | HexagonRegisterInfo.td | 239 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32,
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| D | HexagonISelLowering.cpp | 1550 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba in HexagonTargetLowering()
1788 for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1, in HexagonTargetLowering()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 75 case MVT::v8i1: return "MVT::v8i1"; in getEnumName()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 278 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 }, in getCmpSelInstrCost()
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| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 160 def llvm_v8i1_ty : LLVMType<v8i1>; // 8 x i1
|