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Searched refs:v_add_f32_e64 (Results 1 – 9 of 9) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dllvm.AMDGPU.clamp.ll11 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
24 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, |[[ARG]]| clamp{{$}}
36 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -[[ARG]] clamp{{$}}
48 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -|[[ARG]]| clamp{{$}}
61 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
Dimm.ll131 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0, [[VAL]]{{$}}
141 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}}
151 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}}
161 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}}
171 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}}
181 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}}
191 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}}
201 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}}
211 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}}
243 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1, [[VAL]]{{$}}
[all …]
Dfmul-2-combine-multi-use.ll30 ; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
45 ; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |s{{[0-9]+}}|
Dcommute_modifiers.ll9 ; SI: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, |[[X]]|
54 ; SI: v_add_f32_e64 [[REG:v[0-9]+]], |[[X]]|, [[K]]
69 ; SI: v_add_f32_e64 [[REG:v[0-9]+]], [[X]], |[[Y]]|
Dfneg.ll51 ; XXX: We could use v_add_f32_e64 with the negate bit here instead.
Dcvt_flr_i32_f32.ll21 ; SI: v_add_f32_e64 [[TMP:v[0-9]+]], 1.0, s{{[0-9]+}}
Duse-sgpr-multiple-times.ll12 ; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
/external/llvm/test/MC/AMDGPU/
Dvop3-errs.s4 v_add_f32_e64 v0, v1 label
Dvop3.s174 v_add_f32_e64 v1, v3, v5 label