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Searched refs:val1 (Results 1 – 25 of 320) sorted by relevance

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/external/ceres-solver/internal/ceres/miniglog/glog/
Dlogging.h359 #define CHECK_OP(val1, val2, op) LOG_IF_FALSE(FATAL, ((val1) op (val2))) \ argument
360 << "Check failed: " #val1 " " #op " " #val2 " "
363 #define CHECK_EQ(val1, val2) CHECK_OP(val1, val2, ==) argument
364 #define CHECK_NE(val1, val2) CHECK_OP(val1, val2, !=) argument
365 #define CHECK_LE(val1, val2) CHECK_OP(val1, val2, <=) argument
366 #define CHECK_LT(val1, val2) CHECK_OP(val1, val2, <) argument
367 #define CHECK_GE(val1, val2) CHECK_OP(val1, val2, >=) argument
368 #define CHECK_GT(val1, val2) CHECK_OP(val1, val2, >) argument
372 # define DCHECK_EQ(val1, val2) CHECK_OP(val1, val2, ==) argument
373 # define DCHECK_NE(val1, val2) CHECK_OP(val1, val2, !=) argument
[all …]
/external/llvm/test/CodeGen/ARM/
Dvsel.ll7 %val1 = select i1 %tst1, float %a, float %b
8 store float %val1, float* @varfloat
16 %val1 = select i1 %tst1, double %a, double %b
17 store double %val1, double* @vardouble
25 %val1 = select i1 %tst1, float %a, float %b
26 store float %val1, float* @varfloat
34 %val1 = select i1 %tst1, double %a, double %b
35 store double %val1, double* @vardouble
43 %val1 = select i1 %tst1, float %a, float %b
44 store float %val1, float* @varfloat
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-min-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val2, %val1
11 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val2, %val1
21 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val2, %val1
31 %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
36 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
[all …]
Dvec-max-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val1, %val2
11 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val1, %val2
21 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val1, %val2
31 %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
36 define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
[all …]
Dvec-max-04.ll6 define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp slt <2 x i64> %val1, %val2
11 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
16 define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
20 %cmp = icmp sle <2 x i64> %val1, %val2
21 %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val1
26 define <2 x i64> @f3(<2 x i64> %val1, <2 x i64> %val2) {
30 %cmp = icmp sgt <2 x i64> %val1, %val2
31 %ret = select <2 x i1> %cmp, <2 x i64> %val1, <2 x i64> %val2
36 define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
[all …]
Dvec-min-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val2, %val1
11 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val2, %val1
21 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val2, %val1
31 %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
36 define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
[all …]
Dvec-min-02.ll6 define <8 x i16> @f1(<8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp slt <8 x i16> %val2, %val1
11 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
16 define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
20 %cmp = icmp sle <8 x i16> %val2, %val1
21 %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val1
26 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2) {
30 %cmp = icmp sgt <8 x i16> %val2, %val1
31 %ret = select <8 x i1> %cmp, <8 x i16> %val1, <8 x i16> %val2
36 define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2) {
[all …]
Dvec-max-03.ll6 define <4 x i32> @f1(<4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp slt <4 x i32> %val1, %val2
11 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
16 define <4 x i32> @f2(<4 x i32> %val1, <4 x i32> %val2) {
20 %cmp = icmp sle <4 x i32> %val1, %val2
21 %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val1
26 define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
30 %cmp = icmp sgt <4 x i32> %val1, %val2
31 %ret = select <4 x i1> %cmp, <4 x i32> %val1, <4 x i32> %val2
36 define <4 x i32> @f4(<4 x i32> %val1, <4 x i32> %val2) {
[all …]
Dvec-min-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val2, %val1
11 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val2, %val1
21 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val2, %val1
31 %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
36 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
[all …]
Dvec-max-01.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp slt <16 x i8> %val1, %val2
11 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
16 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
20 %cmp = icmp sle <16 x i8> %val1, %val2
21 %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val1
26 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
30 %cmp = icmp sgt <16 x i8> %val1, %val2
31 %ret = select <16 x i1> %cmp, <16 x i8> %val1, <16 x i8> %val2
36 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
[all …]
Dvec-cmp-03.ll6 define <4 x i32> @f1(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
10 %cmp = icmp eq <4 x i32> %val1, %val2
16 define <4 x i32> @f2(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
21 %cmp = icmp ne <4 x i32> %val1, %val2
27 define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
31 %cmp = icmp sgt <4 x i32> %val1, %val2
37 define <4 x i32> @f4(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
42 %cmp = icmp sge <4 x i32> %val1, %val2
48 define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
53 %cmp = icmp sle <4 x i32> %val1, %val2
[all …]
Dvec-cmp-02.ll6 define <8 x i16> @f1(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
10 %cmp = icmp eq <8 x i16> %val1, %val2
16 define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
21 %cmp = icmp ne <8 x i16> %val1, %val2
27 define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
31 %cmp = icmp sgt <8 x i16> %val1, %val2
37 define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
42 %cmp = icmp sge <8 x i16> %val1, %val2
48 define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
53 %cmp = icmp sle <8 x i16> %val1, %val2
[all …]
Dvec-cmp-01.ll6 define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
10 %cmp = icmp eq <16 x i8> %val1, %val2
16 define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
21 %cmp = icmp ne <16 x i8> %val1, %val2
27 define <16 x i8> @f3(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
31 %cmp = icmp sgt <16 x i8> %val1, %val2
37 define <16 x i8> @f4(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
42 %cmp = icmp sge <16 x i8> %val1, %val2
48 define <16 x i8> @f5(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
53 %cmp = icmp sle <16 x i8> %val1, %val2
[all …]
Dvec-cmp-04.ll6 define <2 x i64> @f1(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
10 %cmp = icmp eq <2 x i64> %val1, %val2
16 define <2 x i64> @f2(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
21 %cmp = icmp ne <2 x i64> %val1, %val2
27 define <2 x i64> @f3(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
31 %cmp = icmp sgt <2 x i64> %val1, %val2
37 define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
42 %cmp = icmp sge <2 x i64> %val1, %val2
48 define <2 x i64> @f5(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
53 %cmp = icmp sle <2 x i64> %val1, %val2
[all …]
Dvec-cmp-06.ll6 define <2 x i64> @f1(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
10 %cmp = fcmp oeq <2 x double> %val1, %val2
16 define <2 x i64> @f2(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
22 %cmp = fcmp one <2 x double> %val1, %val2
28 define <2 x i64> @f3(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
32 %cmp = fcmp ogt <2 x double> %val1, %val2
38 define <2 x i64> @f4(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
42 %cmp = fcmp oge <2 x double> %val1, %val2
48 define <2 x i64> @f5(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) {
52 %cmp = fcmp ole <2 x double> %val1, %val2
[all …]
Dvec-perm-08.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
10 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
19 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
23 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
32 define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
36 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
45 define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
49 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
71 define <8 x i16> @f6(<8 x i16> %val1, <8 x i16> %val2) {
75 %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
[all …]
Dvec-sub-01.ll6 define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
10 %ret = sub <16 x i8> %val1, %val2
15 define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
19 %ret = sub <8 x i16> %val1, %val2
24 define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
28 %ret = sub <4 x i32> %val1, %val2
33 define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
37 %ret = sub <2 x i64> %val1, %val2
45 define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
64 %ret = fsub <4 x float> %val1, %val2
[all …]
/external/valgrind/none/tests/s390x/
Dclgrj.c30 register uint64_t val1 asm("r7") = value1; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
46 register uint64_t val1 asm("r7") = value1; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
62 register uint64_t val1 asm("r7") = value1; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
78 register uint64_t val1 asm("r7") = value1; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
94 register uint64_t val1 asm("r7") = value1; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
Dclrj.c30 register uint32_t val1 asm("r7") = value1; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
46 register uint32_t val1 asm("r7") = value1; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
62 register uint32_t val1 asm("r7") = value1; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
78 register uint32_t val1 asm("r7") = value1; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
94 register uint32_t val1 asm("r7") = value1; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
Dcgrj.c30 register int64_t val1 asm("r7") = value1; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
46 register int64_t val1 asm("r7") = value1; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
62 register int64_t val1 asm("r7") = value1; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
78 register int64_t val1 asm("r7") = value1; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
94 register int64_t val1 asm("r7") = value1; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
Dcrj.c30 register int32_t val1 asm("r7") = value1; in compare_never()
40 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_never()
46 register int32_t val1 asm("r7") = value1; in compare_always()
56 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_always()
62 register int32_t val1 asm("r7") = value1; in compare_le()
72 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_le()
78 register int32_t val1 asm("r7") = value1; in compare_ge()
88 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_ge()
94 register int32_t val1 asm("r7") = value1; in compare_gt()
104 : : "d"(val1), "d"(val2) : "15", BRASLCLOBBER); in compare_gt()
[all …]
/external/llvm/test/CodeGen/AArch64/
Dlogical_shifted_reg.ll11 %val1 = load i32, i32* @var1_32
17 %and_noshift = and i32 %val1, %val2
20 %bic_noshift = and i32 %neg_val2, %val1
24 %or_noshift = or i32 %val1, %val2
27 %orn_noshift = or i32 %neg_val2, %val1
31 %xor_noshift = xor i32 %val1, %val2
34 %xorn_noshift = xor i32 %neg_val2, %val1
42 %and_lsl31 = and i32 %val1, %operand_lsl31
45 %bic_lsl31 = and i32 %val1, %neg_operand_lsl31
49 %or_lsl31 = or i32 %val1, %operand_lsl31
[all …]
/external/elfutils/libdwfl/
Dframe_unwind.c170 Dwarf_Addr val1, val2; in expr_eval() local
218 if (! state_get_reg (state, op->atom - DW_OP_reg0, &val1) in expr_eval()
219 || ! push (val1)) in expr_eval()
226 if (! state_get_reg (state, op->number, &val1) || ! push (val1)) in expr_eval()
233 if (! state_get_reg (state, op->atom - DW_OP_breg0, &val1)) in expr_eval()
238 val1 += op->number; in expr_eval()
239 if (! push (val1)) in expr_eval()
246 if (! state_get_reg (state, op->number, &val1)) in expr_eval()
251 val1 += op->number2; in expr_eval()
252 if (! push (val1)) in expr_eval()
[all …]
/external/libweave/third_party/chromium/base/
Dlogging.h403 #define CHECK_OP(name, op, val1, val2) CHECK((val1) op (val2)) argument
418 #define CHECK_OP(name, op, val1, val2) \ argument
421 logging::Check##name##Impl((val1), (val2), \
422 #val1 " " #op " " #val2)) \
481 #define CHECK_EQ(val1, val2) CHECK_OP(EQ, ==, val1, val2) argument
482 #define CHECK_NE(val1, val2) CHECK_OP(NE, !=, val1, val2) argument
483 #define CHECK_LE(val1, val2) CHECK_OP(LE, <=, val1, val2) argument
484 #define CHECK_LT(val1, val2) CHECK_OP(LT, < , val1, val2) argument
485 #define CHECK_GE(val1, val2) CHECK_OP(GE, >=, val1, val2) argument
486 #define CHECK_GT(val1, val2) CHECK_OP(GT, > , val1, val2) argument
[all …]
/external/regex-re2/util/
Dlogging.h15 #define DCHECK_EQ(val1, val2) assert((val1) == (val2)) argument
16 #define DCHECK_NE(val1, val2) assert((val1) != (val2)) argument
17 #define DCHECK_LE(val1, val2) assert((val1) <= (val2)) argument
18 #define DCHECK_LT(val1, val2) assert((val1) < (val2)) argument
19 #define DCHECK_GE(val1, val2) assert((val1) >= (val2)) argument
20 #define DCHECK_GT(val1, val2) assert((val1) > (val2)) argument

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