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Searched refs:val3 (Results 1 – 25 of 132) sorted by relevance

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/external/strace/
Dfutex.c57 const unsigned int val3 = tcp->u_arg[5]; in SYS_FUNC() local
72 tprintf(", %x", val3); in SYS_FUNC()
75 tprintf(", %x", val3); in SYS_FUNC()
85 tprintf(", %u", val3); in SYS_FUNC()
91 if ((val3 >> 28) & 8) in SYS_FUNC()
93 printxval(futexwakeops, (val3 >> 28) & 0x7, "FUTEX_OP_???"); in SYS_FUNC()
94 tprintf(", %u, ", (val3 >> 12) & 0xfff); in SYS_FUNC()
95 if ((val3 >> 24) & 8) in SYS_FUNC()
97 printxval(futexwakecmps, (val3 >> 24) & 0x7, "FUTEX_OP_CMP_???"); in SYS_FUNC()
98 tprintf(", %u}", val3 & 0xfff); in SYS_FUNC()
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-or-02.ll6 define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
10 %not = xor <16 x i8> %val3, <i8 -1, i8 -1, i8 -1, i8 -1,
14 %and1 = and <16 x i8> %val1, %val3
21 define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
25 %not = xor <16 x i8> %val3, <i8 -1, i8 -1, i8 -1, i8 -1,
30 %and2 = and <16 x i8> %val2, %val3
36 define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
40 %not = xor <8 x i16> %val3, <i16 -1, i16 -1, i16 -1, i16 -1,
42 %and1 = and <8 x i16> %val1, %val3
49 define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
[all …]
Dvec-mul-02.ll9 <16 x i8> %val3) {
14 %ret = add <16 x i8> %mul, %val3
20 <8 x i16> %val3) {
25 %ret = add <8 x i16> %mul, %val3
31 <4 x i32> %val3) {
36 %ret = add <4 x i32> %mul, %val3
42 <2 x double> %val2, <2 x double> %val3) {
48 <2 x double> %val3)
54 <2 x double> %val2, <2 x double> %val3) {
58 %negval3 = fsub <2 x double> <double -0.0, double -0.0>, %val3
Dvec-cmp-03.ll112 <4 x i32> %val3, <4 x i32> %val4) {
118 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
124 <4 x i32> %val3, <4 x i32> %val4) {
130 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
136 <4 x i32> %val3, <4 x i32> %val4) {
142 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
148 <4 x i32> %val3, <4 x i32> %val4) {
154 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
160 <4 x i32> %val3, <4 x i32> %val4) {
166 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
[all …]
Dvec-cmp-02.ll112 <8 x i16> %val3, <8 x i16> %val4) {
118 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
124 <8 x i16> %val3, <8 x i16> %val4) {
130 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
136 <8 x i16> %val3, <8 x i16> %val4) {
142 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
148 <8 x i16> %val3, <8 x i16> %val4) {
154 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
160 <8 x i16> %val3, <8 x i16> %val4) {
166 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
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Dvec-cmp-01.ll112 <16 x i8> %val3, <16 x i8> %val4) {
118 %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
124 <16 x i8> %val3, <16 x i8> %val4) {
130 %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
136 <16 x i8> %val3, <16 x i8> %val4) {
142 %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
148 <16 x i8> %val3, <16 x i8> %val4) {
154 %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
160 <16 x i8> %val3, <16 x i8> %val4) {
166 %ret = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
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Dvec-cmp-04.ll112 <2 x i64> %val3, <2 x i64> %val4) {
118 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
124 <2 x i64> %val3, <2 x i64> %val4) {
130 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
136 <2 x i64> %val3, <2 x i64> %val4) {
142 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
148 <2 x i64> %val3, <2 x i64> %val4) {
154 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
160 <2 x i64> %val3, <2 x i64> %val4) {
166 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
[all …]
Dvec-cmp-06.ll165 <2 x double> %val3, <2 x double> %val4) {
171 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
177 <2 x double> %val3, <2 x double> %val4) {
185 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
191 <2 x double> %val3, <2 x double> %val4) {
197 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
203 <2 x double> %val3, <2 x double> %val4) {
209 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
215 <2 x double> %val3, <2 x double> %val4) {
221 %ret = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
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Dvec-cmp-05.ll308 <4 x float> %val3, <4 x float> %val4) {
314 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
320 <4 x float> %val3, <4 x float> %val4) {
326 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
332 <4 x float> %val3, <4 x float> %val4) {
338 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
344 <4 x float> %val3, <4 x float> %val4) {
350 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
356 <4 x float> %val3, <4 x float> %val4) {
362 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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Dspill-01.ll50 %val3 = load i32 , i32 *%ptr3
60 store i32 %val3, i32 *%ptr3
88 %val3 = load i32 , i32 *%ptr3
100 store i32 %val3, i32 *%ptr3
130 %val3 = load i64 , i64 *%ptr3
142 store i64 %val3, i64 *%ptr3
176 %val3 = load float , float *%ptr3
189 store float %val3, float *%ptr3
220 %val3 = load double , double *%ptr3
233 store double %val3, double *%ptr3
[all …]
Dvec-combine-02.ll114 <4 x i32> %val2, <4 x i32> %val3) {
123 %bitcast3 = bitcast <4 x i32> %val3 to <8 x i16>
142 <4 x i32> %val2, <4 x i32> %val3,
153 %bitcast3 = bitcast <4 x i32> %val3 to <8 x i16>
188 <4 x i32> %val2, <4 x i32> %val3) {
206 %elem12 = extractelement <4 x i32> %val3, i32 0
207 %elem13 = extractelement <4 x i32> %val3, i32 1
208 %elem14 = extractelement <4 x i32> %val3, i32 2
209 %elem15 = extractelement <4 x i32> %val3, i32 3
274 <2 x i64> %val2, <2 x i64> %val3,
[all …]
/external/llvm/test/CodeGen/AArch64/
Dlogical-imm.ll21 %val3 = and i64 %in64, 18429855317404942275
22 store volatile i64 %val3, i64* @var64
43 %val3 = or i64 %in64, 18429855317404942275
44 store volatile i64 %val3, i64* @var64
65 %val3 = xor i64 %in64, 18429855317404942275
66 store volatile i64 %val3, i64* @var64
Dfloatdp_2source.ll13 %val3 = fmul float %val2, %val1
16 %val4 = fdiv float %val3, %val1
41 %val3 = fmul double %val2, %val1
44 %val4 = fdiv double %val3, %val1
Daddsub-shifted.ll23 %val3 = sub i32 %lhs32, %shift3
24 store volatile i32 %val3, i32* @var32
89 %val3 = sub i32 %lhs32, %shift3
90 store volatile i32 %val3, i32* @var32
148 %val3 = sub i32 %lhs32, %shift3
149 store volatile i32 %val3, i32* @var32
266 %val3 = sub i32 0, %shift3
267 %tst3 = icmp eq i32 %lhs32, %val3
Dcompare-branch.ll21 %val3 = load volatile i64, i64* @var64
22 %tst3 = icmp eq i64 %val3, 0
Dregress-w29-reserved-with-fp.ll12 %val3 = load volatile i32, i32* @var
27 store volatile i32 %val3, i32* @var
Dcond-sel.ll81 %val3 = select i1 %tst3, i64 %inc3, i64 %lhs64
82 store volatile i64 %val3, i64* @var64
121 %val3 = select i1 %tst3, i64 %inc3, i64 %lhs64
122 store volatile i64 %val3, i64* @var64
161 %val3 = select i1 %tst3, i64 %inc3, i64 %lhs64
162 store volatile i64 %val3, i64* @var64
/external/llvm/test/CodeGen/X86/
Dx86-mixed-alignment-dagcombine.ll15 %val3 = select i1 %cmp, <2 x double> %val, <2 x double> %val2
16 call void @sink(<2 x double> %val3)
29 %val3 = select i1 %cmp, <2 x double> %val, <2 x double> %val2
30 call void @sink(<2 x double> %val3)
Dconstant-hoisting-cmp.ll19 %val3 = add i64 %data3, 3
23 %p1 = phi i64 [%val1,%entry], [%val2,%L_val2], [%val3,%L_val3]
/external/valgrind/memcheck/tests/darwin/
Denv.c12 char* val3 = "xxx"; in main() local
20 setenv("MYVAR", val3, /*overwrite*/0); // doesn't overwrite MYVAR=val2 in main()
/external/llvm/test/CodeGen/NVPTX/
Dsched1.ll21 %val3 = load i32, i32* %ptr3
25 %t2 = add i32 %t1, %val3
Dsched2.ll22 %val3 = load <2 x i32>, <2 x i32>* %ptr3
26 %t2 = add <2 x i32> %t1, %val3
/external/libbrillo/brillo/
Dany_unittest.cc23 Any val3 = std::move(val); in TEST() local
25 EXPECT_TRUE(val3.IsEmpty()); in TEST()
40 Any val3(std::string("blah")); in TEST() local
41 EXPECT_TRUE(val3.IsTypeCompatible<std::string>()); in TEST()
42 EXPECT_EQ("blah", val3.Get<std::string>()); in TEST()
/external/llvm/test/CodeGen/ARM/
Dgpr-paired-spill-thumbinst.ll11 %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
24 store volatile i64 %val3, i64* %addr
Dinlineasm-64bit.ll13 define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6…
37 …$6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %va…
39 …}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %va…
40 …}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %va…

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