| /external/libavc/common/arm/ |
| D | ih264_inter_pred_luma_bilinear_a9q.s | 136 vld1.8 {q0}, [r0], r3 @// Load row0 ;src1
137 vld1.8 {q2}, [r1], r4 @// Load row0 ;src2
138 vld1.8 {q1}, [r0], r3 @// Load row1 ;src1
140 vld1.8 {q3}, [r1], r4 @// Load row1 ;src2
142 vld1.8 {q4}, [r0], r3 @// Load row2 ;src1
144 vld1.8 {q5}, [r0], r3 @// Load row3 ;src1
146 vld1.8 {q6}, [r1], r4 @// Load row2 ;src2
148 vld1.8 {q7}, [r1], r4 @// Load row3 ;src2
159 vld1.8 {q0}, [r0], r3 @// Load row4 ;src1
161 vld1.8 {q1}, [r0], r3 @// Load row5 ;src1
[all …]
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| D | ih264_default_weighted_pred_a9q.s | 124 vld1.32 d0[0], [r0], r3 @load row 1 in source 1
125 vld1.32 d0[1], [r0], r3 @load row 2 in source 1
126 vld1.32 d2[0], [r1], r4 @load row 1 in source 2
127 vld1.32 d2[1], [r1], r4 @load row 2 in source 2
129 vld1.32 d1[0], [r0], r3 @load row 3 in source 1
130 vld1.32 d1[1], [r0], r3 @load row 4 in source 1
132 vld1.32 d3[0], [r1], r4 @load row 3 in source 2
133 vld1.32 d3[1], [r1], r4 @load row 4 in source 2
148 vld1.8 d0, [r0], r3 @load row 1 in source 1
149 vld1.8 d4, [r1], r4 @load row 1 in source 2
[all …]
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| /external/llvm/test/MC/ARM/ |
| D | neon-vld-encoding.s | 3 vld1.8 {d16}, [r0:64]
4 vld1.16 {d16}, [r0]
5 vld1.32 {d16}, [r0]
6 vld1.64 {d16}, [r0]
7 vld1.8 {d16, d17}, [r0:64]
8 vld1.16 {d16, d17}, [r0:128]
9 vld1.32 {d16, d17}, [r0]
10 vld1.64 {d16, d17}, [r0]
11 vld1.8 {d1, d2, d3}, [r3]
12 vld1.16 {d4, d5, d6}, [r3:64]
[all …]
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| D | neont2-vld-encoding.s | 5 @ CHECK: vld1.8 {d16}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x07]
6 vld1.8 {d16}, [r0:64]
7 @ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x60,0xf9,0x4f,0x07]
8 vld1.16 {d16}, [r0]
9 @ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x60,0xf9,0x8f,0x07]
10 vld1.32 {d16}, [r0]
11 @ CHECK: vld1.64 {d16}, [r0] @ encoding: [0x60,0xf9,0xcf,0x07]
12 vld1.64 {d16}, [r0]
13 @ CHECK: vld1.8 {d16, d17}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x0a]
14 vld1.8 {d16, d17}, [r0:64]
[all …]
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| /external/libmpeg2/common/arm/ |
| D | impeg2_inter_pred.s | 109 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
113 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
115 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
117 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
119 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
121 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
123 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
125 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
127 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
129 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
[all …]
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| D | impeg2_idct.s | 127 vld1.8 d0, [r2], r1
130 vld1.8 d1, [r2], r1
133 vld1.8 d2, [r2], r1
141 vld1.8 d3, [r2], r1
144 vld1.8 d4, [r2], r1
147 vld1.8 d5, [r2], r1
150 vld1.8 d6, [r2], r1
154 vld1.8 d7, [r2], r1
225 vld1.16 {q1}, [r4], r14
227 vld1.8 d30, [r2], r1
[all …]
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | neont-VLD-reencoding.txt | 12 # CHECK: vld1.8 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x00]
13 # CHECK: vld1.8 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x00]
14 # CHECK: vld1.8 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x00]
15 # CHECK: vld1.8 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0x60,0x00]
16 # CHECK: vld1.8 {d0[4]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x00]
17 # CHECK: vld1.8 {d0[5]}, [r0], r0 @ encoding: [0xa0,0xf9,0xa0,0x00]
18 # CHECK: vld1.8 {d0[6]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x00]
19 # CHECK: vld1.8 {d0[7]}, [r0], r0 @ encoding: [0xa0,0xf9,0xe0,0x00]
30 # CHECK: vld1.16 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x04]
31 # CHECK: vld1.16 {d0[0]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x10,0x04]
[all …]
|
| /external/libhevc/common/arm/ |
| D | ihevc_intra_pred_luma_mode_18_34.s | 133 vld1.8 {d0},[r8],r6
135 vld1.8 {d1},[r8],r6
137 vld1.8 {d2},[r8],r6
138 vld1.8 {d3},[r8],r6
140 vld1.8 {d4},[r8],r6
141 vld1.8 {d5},[r8],r6
142 vld1.8 {d6},[r8],r6
144 vld1.8 {d7},[r8],r6
164 vld1.8 {d0},[r8],r6
168 vld1.8 {d1},[r8],r6
[all …]
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| D | ihevc_inter_pred_chroma_horz.s | 114 vld1.8 {d0},[r4] @coeff = vld1_s8(pi1_coeff)
161 vld1.u32 {q0},[r12],r11 @vector load pu1_src
163 vld1.u32 {q1},[r12],r11 @vector load pu1_src
165 vld1.u32 {q2},[r12],r11 @vector load pu1_src
167 vld1.u32 {q3},[r12],r9 @vector load pu1_src
171 vld1.u32 {q4},[r4],r11 @vector load pu1_src
173 vld1.u32 {q5},[r4],r11 @vector load pu1_src
175 vld1.u32 {q6},[r4],r11 @vector load pu1_src
177 vld1.u32 {q7},[r4],r9 @vector load pu1_src
218 vld1.u32 {q0},[r12],r11 @vector load pu1_src
[all …]
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| D | ihevc_intra_pred_luma_mode2.s | 122 vld1.8 {d0},[r0],r8
125 vld1.8 {d1},[r10],r8
128 vld1.8 {d2},[r0],r8
129 vld1.8 {d3},[r10],r8
132 vld1.8 {d4},[r0],r8
133 vld1.8 {d5},[r10],r8
134 vld1.8 {d6},[r0],r8
137 vld1.8 {d7},[r10],r8
178 vld1.8 {d0},[r0],r8
181 vld1.8 {d1},[r10],r8
[all …]
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| D | ihevc_inter_pred_chroma_horz_w16out.s | 113 vld1.8 {d0},[r4] @coeff = vld1_s8(pi1_coeff)
178 vld1.u32 {q0},[r12],r11 @vector load pu1_src
181 vld1.u32 {q1},[r12],r11 @vector load pu1_src
184 vld1.u32 {q2},[r12],r11 @vector load pu1_src
187 vld1.u32 {q3},[r12],r9 @vector load pu1_src
191 vld1.u32 {q4},[r4],r11 @vector load pu1_src
193 vld1.u32 {q5},[r4],r11 @vector load pu1_src
195 vld1.u32 {q6},[r4],r11 @vector load pu1_src
197 vld1.u32 {q7},[r4],r9 @vector load pu1_src
238 vld1.u32 {q0},[r12],r11 @vector load pu1_src
[all …]
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| D | ihevc_inter_pred_luma_horz_w16out.s | 129 vld1.8 {d0},[r4] @coeff = vld1_s8(pi1_coeff)
202 vld1.u32 {d0},[r12],r11 @vector load pu1_src
203 vld1.u32 {d1},[r12],r11
204 vld1.u32 {d2},[r12],r11
205 vld1.u32 {d3},[r12],r11
206 vld1.u32 {d4},[r12],r11
207 vld1.u32 {d5},[r12],r11
208 vld1.u32 {d6},[r12],r11
209 vld1.u32 {d7},[r12],r11
220 vld1.u32 {d12},[r4],r11 @vector load pu1_src + src_strd
[all …]
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| D | ihevc_inter_pred_filters_luma_horz.s | 129 vld1.8 {d0},[r4] @coeff = vld1_s8(pi1_coeff)
191 vld1.u32 {d0},[r12],r11 @vector load pu1_src
192 vld1.u32 {d1},[r12],r11
193 vld1.u32 {d2},[r12],r11
194 vld1.u32 {d3},[r12],r11
215 vld1.u32 {d4},[r12],r11
217 vld1.u32 {d5},[r12],r11
219 vld1.u32 {d6},[r12],r11
221 vld1.u32 {d7},[r12],r11
223 vld1.u32 {d12},[r4],r11 @vector load pu1_src + src_strd
[all …]
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| D | ihevc_itrans_recon_32x32.s | 171 vld1.16 {d0,d1,d2,d3},[r14]!
172 vld1.16 {d4,d5,d6,d7},[r14]!
206 vld1.16 d10,[r0],r6
207 vld1.16 d8,[r0],r6
208 vld1.16 d11,[r0],r6
209 vld1.16 d9,[r0],r6
240 vld1.16 d12,[r0],r6
241 vld1.16 d14,[r0],r6
242 vld1.16 d13,[r0],r6
243 vld1.16 d15,[r0],r6
[all …]
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| D | ihevc_intra_pred_chroma_mode_18_34.s | 134 vld1.8 {d0,d1},[r8],r6
136 vld1.8 {d2,d3},[r8],r6
138 vld1.8 {d4,d5},[r8],r6
140 vld1.8 {d6,d7},[r8],r6
142 vld1.8 {d8,d9},[r8],r6
144 vld1.8 {d10,d11},[r8],r6
146 vld1.8 {d12,d13},[r8],r6
148 vld1.8 {d14,d15},[r8],r6
171 vld1.8 {d0},[r0],r8
174 vld1.8 {d0},[r0],r8
[all …]
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| D | ihevc_inter_pred_chroma_vert_w16out.s | 115 vld1.8 {d0},[r12] @loads pi1_coeff
142 vld1.8 {d9},[r6],r2 @loads pu1_src
144 vld1.8 {d5},[r0]! @loads src
146 vld1.8 {d4},[r6],r2 @loads incremented src
148 vld1.8 {d8},[r6],r2 @loads incremented src
151 vld1.8 {d10},[r6] @loads the incremented src
182 vld1.32 {d6[0]},[r0] @vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp1, 0
185 vld1.32 {d6[1]},[r6],r2 @loads pu1_src_tmp
187 vld1.32 {d7[1]},[r6],r2 @loads pu1_src_tmp
190 vld1.32 {d7[1]},[r6],r2
[all …]
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| D | ihevc_inter_pred_filters_luma_vert.s | 123 vld1.u8 {d0},[r12] @coeff = vld1_s8(pi1_coeff)
154 vld1.u8 {d1},[r3],r2 @src_tmp2 = vld1_u8(pu1_src_tmp)@
155 vld1.u8 {d0},[r0]! @src_tmp1 = vld1_u8(pu1_src_tmp)@
157 vld1.u8 {d2},[r3],r2 @src_tmp3 = vld1_u8(pu1_src_tmp)@
159 vld1.u8 {d3},[r3],r2 @src_tmp4 = vld1_u8(pu1_src_tmp)@
161 vld1.u8 {d4},[r3],r2 @src_tmp1 = vld1_u8(pu1_src_tmp)@
163 vld1.u8 {d5},[r3],r2 @src_tmp2 = vld1_u8(pu1_src_tmp)@
165 vld1.u8 {d6},[r3],r2 @src_tmp3 = vld1_u8(pu1_src_tmp)@
167 vld1.u8 {d7},[r3],r2 @src_tmp4 = vld1_u8(pu1_src_tmp)@
169 vld1.u8 {d16},[r3],r2 @src_tmp1 = vld1_u8(pu1_src_tmp)@
[all …]
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| D | ihevc_intra_pred_filters_luma_mode_19_to_25.s | 151 vld1.32 d0[0],[r1]! @ pu1_ref[two_nt + k]
165 vld1.8 d0,[r1]!
166 vld1.8 d1,[r1]!
167 vld1.8 d2,[r1]!
168 vld1.8 d3,[r1]!
177 vld1.8 d0,[r1]!
178 vld1.8 d1,[r1]!
185 vld1.8 d0,[r1]!
260 vld1.8 {d3},[r6] @loads the row value
276 vld1.8 {d8},[r10],r11 @(i row)ref_main_idx
[all …]
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| /external/llvm/test/CodeGen/ARM/ |
| D | vld1.ll | 9 ;CHECK: vld1.8 {d16}, [r0:64]
10 %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %A, i32 16)
16 ;CHECK: vld1.16
18 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %tmp0, i32 1)
25 ;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
28 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %tmp0, i32 1)
36 ;CHECK: vld1.32
38 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8* %tmp0, i32 1)
45 ;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
48 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8* %tmp0, i32 1)
[all …]
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| /external/libvpx/libvpx/vpx_dsp/arm/ |
| D | vpx_convolve_avg_neon_asm.asm | 36 vld1.8 {q0-q1}, [r0]!
37 vld1.8 {q2-q3}, [r0], lr
39 vld1.8 {q8-q9}, [r6@128]!
40 vld1.8 {q10-q11}, [r6@128], r4
52 vld1.8 {q0-q1}, [r0], r1
53 vld1.8 {q2-q3}, [r0], r1
54 vld1.8 {q8-q9}, [r6@128], r3
55 vld1.8 {q10-q11}, [r6@128], r3
71 vld1.8 {q0}, [r0], r1
72 vld1.8 {q1}, [r0], r1
[all …]
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| D | idct16x16_1_add_neon.asm | 52 vld1.64 {d2}, [r1], r0
53 vld1.64 {d3}, [r1], r2
54 vld1.64 {d4}, [r1], r0
55 vld1.64 {d5}, [r1], r2
56 vld1.64 {d6}, [r1], r0
57 vld1.64 {d7}, [r1], r2
58 vld1.64 {d16}, [r1], r0
59 vld1.64 {d17}, [r1], r2
88 vld1.64 {d2}, [r1], r0
89 vld1.64 {d3}, [r1], r2
[all …]
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| D | vpx_convolve8_avg_neon_asm.asm | 61 vld1.s16 {q0}, [r5] ; filter_x
76 vld1.8 {d24}, [r0], r1
77 vld1.8 {d25}, [r0], r1
78 vld1.8 {d26}, [r0], r1
79 vld1.8 {d27}, [r0], r8
101 vld1.32 {d28[]}, [r0], r1
102 vld1.32 {d29[]}, [r0], r1
103 vld1.32 {d31[]}, [r0], r1
104 vld1.32 {d30[]}, [r0], r8
123 vld1.u32 {d6[0]}, [r2], r3
[all …]
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| /external/libavc/encoder/arm/ |
| D | ime_distortion_metrics_a9q.s | 98 vld1.8 {d4, d5}, [r0], r2
99 vld1.8 {d6, d7}, [r1], r3
101 vld1.8 {d8, d9}, [r0], r2
104 vld1.8 {d10, d11}, [r1], r3
108 vld1.8 {d4, d5}, [r0], r2
111 vld1.8 {d6, d7}, [r1], r3
113 vld1.8 {d8, d9}, [r0], r2
116 vld1.8 {d10, d11}, [r1], r3
180 vld1.8 {d4, d5}, [r0], r2
181 vld1.8 {d6, d7}, [r1], r3
[all …]
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| /external/boringssl/linux-arm/crypto/aes/ |
| D | bsaes-armv7.S | 20 @ it can be compiled for either endianness] by courtesy of vld1.8's
1132 vld1.8 {q15}, [r8] @ load IV
1140 vld1.8 {q0,q1}, [r0]! @ load input
1141 vld1.8 {q2,q3}, [r0]!
1147 vld1.8 {q4,q5}, [r0]!
1149 vld1.8 {q6,q7}, [r0]
1156 vld1.8 {q8,q9}, [r0]! @ reload input
1158 vld1.8 {q10,q11}, [r0]!
1161 vld1.8 {q12,q13}, [r0]!
1164 vld1.8 {q14,q15}, [r0]!
[all …]
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| D | aesv8-armx32.S | 37 vld1.8 {q3},[r0]!
39 vld1.32 {q1,q2},[r3]!
64 vld1.32 {q1},[r3]
102 vld1.8 {d16},[r0]!
138 vld1.8 {q8},[r0]
199 vld1.32 {q0},[r2]
200 vld1.32 {q1},[r0]
205 vld1.32 {q0},[r2]
206 vld1.32 {q1},[r0]
214 vld1.32 {q0},[r2]
[all …]
|