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Searched refs:writes (Results 1 – 25 of 398) sorted by relevance

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/external/llvm/test/MC/Mips/
Dmips-reginfo-fp32.s25 # abs.s - Reads and writes from/to $f0.
27 # round.w.d - Reads $f4 and $f5 and writes to $f2.
29 # ceil.w.s - Reads $f8 and writes to $f10.
31 # cvt.s.d - Reads from $f12 and $f13 and writes to $f14
33 # abs.d - Reads from $f30 and $f31 and writes to $f30 and $f31.
Dmips-reginfo-fp64.s47 # abs.s - Reads and writes from/to $f0.
49 # round.w.d - Reads $f4 and writes to $f2.
51 # ceil.w.s - Reads $f8 and writes to $f10.
53 # cvt.s.d - Reads from $f12 and writes to $f14.
55 # abs.d - Reads from $f30 and writes to $f30.
/external/deqp/external/vulkancts/framework/vulkan/
DvkBuilderUtil.cpp224 std::vector<VkWriteDescriptorSet> writes = m_writes; in update() local
231 writes[writeNdx].pImageInfo = &writeInfo.imageInfos[0]; in update()
234 writes[writeNdx].pBufferInfo = &writeInfo.bufferInfos[0]; in update()
237 writes[writeNdx].pTexelBufferView = &writeInfo.texelBufferViews[0]; in update()
240 const VkWriteDescriptorSet* const writePtr = (m_writes.empty()) ? (DE_NULL) : (&writes[0]); in update()
243 …vk.updateDescriptorSets(device, (deUint32)writes.size(), writePtr, (deUint32)m_copies.size(), copy… in update()
/external/chromium-trace/catapult/telemetry/telemetry/web_perf/metrics/
Dblob_timeline.py61 writes = []
66 writes.append(self.ThreadDurationIfPresent(event))
67 if writes:
73 values=writes,
/external/deqp/doc/testspecs/GLES3/
Dfunctional.occlusion_query.txt27 - Depth writes and clears
28 - Stencil writes and clears
40 boxes, depth writes/clears or stencil writes/clears. Second, a number of
Dfunctional.rasterizer_discard.txt27 - Color clears & writes
28 - Depth clears & writes
29 - Stencil clears & writes
/external/fio/t/jobs/
Dt0008-ae2fafc8.fio1 # Expected result: fio writes 16MB, reads 16+16MB
2 # Buggy result: fio writes 16MB, reads ~21MB
Dt0005-f7078f7b.fio1 # Expected result: fio reads and writes 100m
2 # Buggy result: fio reads and writes ~100m/2
/external/llvm/bindings/ocaml/bitwriter/
Dllvm_bitwriter.mli15 (** [write_bitcode_file m path] writes the bitcode for module [m] to the file at
21 (** [write_bitcode_to_fd ~unbuffered fd m] writes the bitcode for module
34 (** [output_bitcode ~unbuffered c m] writes the bitcode for module [m]
/external/valgrind/none/tests/s390x/
Dexrl.stdout.exp8 ------- EXRL 0,... has no effect (writes out target)
11 ------- EXRL to OR in the syscall number (writes out target)
Dex.stdout.exp8 ------- EX 0,... has no effect (writes out target)
11 ------- EX to OR in the syscall number (writes out target)
/external/llvm/lib/CodeGen/
DCalcSpillWeights.cpp171 bool reads, writes; in calculateSpillWeightAndHint() local
172 std::tie(reads, writes) = mi->readsWritesVirtualRegister(li.reg); in calculateSpillWeightAndHint()
174 writes, reads, &MBFI, mi); in calculateSpillWeightAndHint()
177 if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb)) in calculateSpillWeightAndHint()
/external/autotest/client/tests/fsstress/
Dcontrol9 random web server ones. It writes about 24MB/s but has many small writes a
/external/autotest/client/tests/iosched_bugs/
Dcontrol9 reads or writes can be starved when switching a batch and a request from the
10 previous batch is still in-flight. This test case should see writes being
/external/llvm/include/llvm/Target/
DTargetSchedule.td201 // operand that both reads and writes a reg. In both cases we have a
220 // Variadic, then the list of prior writes are distributed across all
224 class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
225 list<SchedWrite> Writes = writes;
271 // should define one of the writes to be zero micro-ops. If a
274 // or require additional writes. Extra writes can be required either
275 // by defining a WriteSequence, or simply listing extra writes in the
294 class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> {
296 list<SchedWrite> ValidWrites = writes;
313 class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>
[all …]
/external/libchrome/base/process/
Dprocess_metrics_linux.cc760 writes = 0; in SystemDiskInfo()
778 res->SetDouble("writes", static_cast<double>(writes)); in ToValue()
839 diskinfo->writes = 0; in GetSystemDiskInfo()
851 uint64_t writes = 0; in GetSystemDiskInfo() local
869 StringToUint64(disk_fields[kDiskWrites], &writes); in GetSystemDiskInfo()
881 diskinfo->writes += writes; in GetSystemDiskInfo()
/external/fio/
Diolog.c334 int reads, writes, waits, fileno = 0, file_action = 0; /* stupid gcc */ in read_iolog2() local
349 reads = writes = waits = 0; in read_iolog2()
408 writes++; in read_iolog2()
442 if (writes && read_only) { in read_iolog2()
444 " read-only\n", td->o.name, writes); in read_iolog2()
445 writes = 0; in read_iolog2()
448 if (!reads && !writes && !waits) in read_iolog2()
450 else if (reads && !writes) in read_iolog2()
452 else if (!reads && writes) in read_iolog2()
/external/autotest/client/tests/kvm/scripts/
Dvirtio_console_guest.py618 writes = 0
624 writes = os.write(in_f[0], data)
631 while (writes < length):
633 writes += os.write(in_f[0], data)
636 if writes >= length:
637 print "PASS: Send data length %d" % writes
640 (length, writes))
/external/strace/
Dquota.c211 u_int32_t writes; member
223 u_int32_t writes; member
396 tprintf("writes=%u, ", dq.writes); in decode_cmd_data()
412 tprintf("writes=%u, ", dq.writes); in decode_cmd_data()
/external/gemmlowp/meta/
DREADME50 aligned memory reads/writes and unaligned memory reads/writes.
58 for leftover handling. Finally aligned memory reads/writes are used everywhere
/external/skia/src/gpu/
DGrStencil.h270 bool writes = GR_STENCIL_SETTINGS_DOES_WRITE( in doesWrite() local
274 fFlags |= writes ? kDoesWrite_StencilFlag : kDoesNotWrite_StencilFlag; in doesWrite()
275 return writes; in doesWrite()
/external/autotest/client/tests/ffsb/
Dprofile.cfg.sample1 # Large file random writes.
/external/autotest/client/tests/ddtest/
Dcontrol6 in disk writes.
/external/autotest/client/site_tests/platform_CryptohomeFio/
D8k_write5 ; 8k random writes over a 1 GiB area.
D4k_write5 ; 4k random writes over a 1 GiB area.

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