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Searched refs:zA (Results 1 – 25 of 219) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
D	arm64-codegen-prepare-extload.ll	9 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p 10 ; OPTALL-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 29 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p 30 ; OPT-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 31 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2 33 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2 34 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32 55 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p 56 ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32 57 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2 [all …]
D	aarch64-gep-opt.ll	39 ; CHECK-NoAA: [[PTR0:%[a-zA-Z0-9]+]] = ptrtoint [240 x %struct]* %string to i64 40 ; CHECK-NoAA: [[PTR1:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 41 ; CHECK-NoAA: [[PTR2:%[a-zA-Z0-9]+]] = add i64 [[PTR0]], [[PTR1]] 51 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = bitcast [240 x %struct]* %string to i8* 52 ; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 53 ; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8, i8* [[PTR0]], i64 [[IDX]] 93 ; CHECK-NoAA: add i64 [[TMP:%[a-zA-Z0-9]+]], 528 96 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 532 98 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 528 101 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr [all …]
/external/icu/icu4c/source/config/
D	make2sh.sed	`2 s%^$[a-zA-Z0-9\._-]$[ ]+=%\1=$(\1) % 8 s@^[a-zA-Z%$.][^=]$@#M#&@ 9 s@^$[a-zA-Z][-.a-zA-Z_0-9-]$[ ]=[ ]$.$@\1="\2"@ 10 s@^$[a-zA-Z][-a-zA-Z_0-9-]$\.$[a-zA-Z_0-9-]$[ ]=[ ]$.$@\1_\2=\3@ 11 s@^$[a-zA-Z][-a-zA-Z_0-9-]$\-$[a-zA-Z_0-9-]$[ ]=[ ]$.$@\1_\2=\3@ 12 s@\${$[a-zA-Z][-a-zA-Z_0-9-]$\.$[a-zA-Z_0-9-]*$}@${\1_\2}@g`
/external/llvm/test/CodeGen/X86/
D	codegen-prepare-extload.ll	15 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p 16 ; OPTALL-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 35 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p 36 ; OPT-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 37 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2 39 ; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2 40 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32 61 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p 62 ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32 63 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2 [all …]
D	codegen-prepare-addrmode-sext.ll	14 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg1 to i64 15 ; CHECK: [[ARG2SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg2 to i64 16 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], [[ARG2SEXT]] 58 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg1 to i64 59 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1 72 ; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 %arg1 to i64 73 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1ZEXT]], 1 93 ; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 0, 1 108 ; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 %arg1 to i8 109 ; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64 [all …]
/external/llvm/test/CodeGen/ARM/
D	vector-promotion.ll	6 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 7 ; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 undef, i32 1> 8 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[VECTOR_OR]], i32 1 27 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 28 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0 29 ; IR-BOTH-NEXT: [[CMP:%[a-zA-Z_0-9-]+]] = icmp eq i32 [[EXTRACT]], %in2 47 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 48 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0 51 ; IR-BOTH: [[OR:%[a-zA-Z_0-9-]+]] = or i32 [[EXTRACT]], 1 73 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1 [all …]
/external/icu/icu4c/source/test/testdata/
D	regextst.txt	1327 "^[a-zA-Z]{1,2}[0-9][0-9A-Za-z]{0,1} {0,1}[0-9][A-Za-z]{2}$" G "<0>G1 1AA</0>" 1328 "^[a-zA-Z]{1,2}[0-9][0-9A-Za-z]{0,1} {0,1}[0-9][A-Za-z]{2}$" G "<0>EH10 2QQ</0>" 1329 "^[a-zA-Z]{1,2}[0-9][0-9A-Za-z]{0,1} {0,1}[0-9][A-Za-z]{2}$" G "<0>SW1 1ZZ</0>" 1330 "^[a-zA-Z]{1,2}[0-9][0-9A-Za-z]{0,1} {0,1}[0-9][A-Za-z]{2}$" "G111 1AA" 1331 "^[a-zA-Z]{1,2}[0-9][0-9A-Za-z]{0,1} {0,1}[0-9][A-Za-z]{2}$" "X10 WW" 1332 "^[a-zA-Z]{1,2}[0-9][0-9A-Za-z]{0,1} {0,1}[0-9][A-Za-z]{2}$" "DDD 5WW" 1333 #"^[\w\-]+(?:\.[\w\-]+)@(?:[\w\-]+\.)+[a-zA-Z]{2,7}$" dG "<0>joe.tillis@unit.army.mil</0>" # T… 1334 #"^[\w-]+(?:\.[\w-]+)@(?:[\w-]+\.)+[a-zA-Z]{2,7}$" G "<0>jack_rabbit@slims.com</0>" # TODO: \… 1335 #"^[\w-]+(?:\.[\w-]+)@(?:[\w-]+\.)+[a-zA-Z]{2,7}$" G "<0>foo99@foo.co.uk</0>" # TODO: \w in p… 1336 #"^[\w-]+(?:\.[\w-]+)@(?:[\w-]+\.)+[a-zA-Z]{2,7}$" "find_the_mistake.@foo.org" # TODO: \w i… [all …]
/external/llvm/test/CodeGen/CPP/
D	atomic.ll	5 …; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xchg, {{.}}, Se… 10 …; CHECK: AtomicRMWInst [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Add, {{.}}, Seq… 15 …; CHECK: AtomicRMWInst [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Sub, {{.}}, Mon… 20 …; CHECK: AtomicRMWInst [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::And, {{.}}, Acq… 25 …; CHECK: AtomicRMWInst [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Nand, {{.}}, Re… 30 …; CHECK: AtomicRMWInst [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Or, {{.}}, Sequ… 35 …; CHECK: AtomicRMWInst [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xor, {{.}}, Rel… 40 …; CHECK: AtomicRMWInst [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Max, {{.}}, Mon… 45 …; CHECK: AtomicRMWInst [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Min, {{.}}, Acq… 50 …; CHECK: AtomicRMWInst [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMax, {{.*}}, Mo… [all …]
/external/llvm/test/Transforms/InstCombine/
D	select-cmp-cttz-ctlz.ll	9 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false) 20 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false) 31 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false) 42 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false) 53 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false) 64 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false) 75 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false) 86 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 false) 97 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 false) 108 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false) [all …]
/external/clang/test/CodeGenObjCXX/
D	literals.mm	19 // CHECK: [[ARR:%[a-zA-Z0-9.]+]] = alloca i8* 20 // CHECK: [[OBJECTS:%[a-zA-Z0-9.]+]] = alloca [2 x i8] 25 …// CHECK: [[ELEMENT0:%[a-zA-Z0-9.]+]] = getelementptr inbounds [2 x i8], [2 x i8] [[OBJECTS]], … 27 // CHECK-NEXT: [[OBJECT0:%[a-zA-Z0-9.]+]] = invoke i8* @_ZNK1XcvP11objc_objectEv 28 // CHECK: [[RET0:%[a-zA-Z0-9.]+]] = call i8* @objc_retainAutoreleasedReturnValue(i8* [[OBJECT0]]) 32 …// CHECK: [[ELEMENT1:%[a-zA-Z0-9.]+]] = getelementptr inbounds [2 x i8], [2 x i8]* [[OBJECTS]], … 34 // CHECK: [[OBJECT1:%[a-zA-Z0-9.]+]] = invoke i8* @_ZNK1YcvP11objc_objectEv 35 // CHECK: [[RET1:%[a-zA-Z0-9.]+]] = call i8* @objc_retainAutoreleasedReturnValue(i8* [[OBJECT1]]) 71 // CHECK: [[ARR:%[a-zA-Z0-9.]+]] = alloca i8* 72 // CHECK: [[OBJECTS:%[a-zA-Z0-9.]+]] = alloca [2 x i8*] [all …]
/external/llvm/test/Transforms/StraightLineStrengthReduce/
D	slsr-add.ll	8 ; [[BASIS:%[a-zA-Z0-9]+]] = add i32 %b, %s 22 ; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %b, %s2 26 ; CHECK: [[t2:%[a-zA-Z0-9]+]] = add i32 [[t1]], %s2 38 ; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %s, %b 42 ; CHECK: [[bump:%[a-zA-Z0-9]+]] = mul i32 %s, 3 43 ; CHECK: [[t2:%[a-zA-Z0-9]+]] = add i32 [[t1]], [[bump]] 67 ; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %b, %s6 72 ; CHECK: [[bump:%[a-zA-Z0-9]+]] = shl i32 %s, 1 73 ; CHECK: [[t2:%[a-zA-Z0-9]+]] = sub i32 [[t1]], [[bump]] 78 ; CHECK: [[t3:%[a-zA-Z0-9]+]] = sub i32 [[t2]], [[bump]] [all …]
/external/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/
D	split-gep.ll	27 ; CHECK: getelementptr [1024 x %struct.S], [1024 x %struct.S]* @struct_array, i64 0, i64 %{{[a-zA-Z… 46 … float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} 47 ; CHECK: getelementptr inbounds float, float* %{{[a-zA-Z0-9]+}}, i64 32 67 …ASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array,… 92 …E_PTR_1:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array,… 94 …E_PTR_2:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array,… 112 …ASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array,… 127 … CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @floa… 146 ; CHECK: getelementptr inbounds float, float* %{{[a-zA-Z0-9]+}}, i64 8 156 ; CHECK: %[[j2:[a-zA-Z0-9]+]] = sub i64 0, %j [all …]
D	split-gep-and-gvn.ll	`54 …:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @… 97 …:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @… 147 …:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @… 193 …:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @…`
/external/llvm/test/CodeGen/PowerPC/
D	ppc64-gep-opt.ll	33 ; CHECK-NoAA: [[PTR0:%[a-zA-Z0-9]+]] = ptrtoint [240 x %struct]* %string to i64 34 ; CHECK-NoAA: [[PTR1:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 35 ; CHECK-NoAA: [[PTR2:%[a-zA-Z0-9]+]] = add i64 [[PTR0]], [[PTR1]] 45 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = bitcast [240 x %struct]* %string to i8* 46 ; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 47 ; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8, i8* [[PTR0]], i64 [[IDX]] 84 ; CHECK-NoAA: add i64 [[TMP:%[a-zA-Z0-9]+]], 528 87 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 532 89 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 528 92 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr [all …]
D	ppc64-toc.ll	`63 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} 65 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} 67 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} 69 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}`
D	2012-09-16-TOC-entry-check.ll	`25 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} 27 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}`
/external/llvm/test/Transforms/LoopVectorize/
D	if-pred-stores.ll	65 ; UNROLL: %[[IND:[a-zA-Z0-9]+]] = add i64 %{{.}}, 0 66 ; UNROLL: %[[IND1:[a-zA-Z0-9]+]] = add i64 %{{.}}, 1 67 ; UNROLL: %[[v0:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND]] 68 ; UNROLL: %[[v1:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND1]] 69 ; UNROLL: %[[v2:[a-zA-Z0-9]+]] = load i32, i32* %[[v0]], align 4 70 ; UNROLL: %[[v3:[a-zA-Z0-9]+]] = load i32, i32* %[[v1]], align 4 71 ; UNROLL: %[[v4:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v2]], 100 72 ; UNROLL: %[[v5:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v3]], 100 73 ; UNROLL: %[[v6:[a-zA-Z0-9]+]] = add nsw i32 %[[v2]], 20 74 ; UNROLL: %[[v7:[a-zA-Z0-9]+]] = add nsw i32 %[[v3]], 20 [all …]
/external/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/
D	split-gep-and-gvn-addrspace-addressing-modes.ll	8 …[a-zA-Z0-9]+]] = getelementptr inbounds [4096 x [32 x float]], [4096 x [32 x float]] addrspace(2)… 40 …%[a-zA-Z0-9]+]] = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(2) … 43 …]], [4096 x [4 x float]] addrspace(2)* @array2, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} 44 …]], [4096 x [4 x float]] addrspace(2)* @array2, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} 73 …a-zA-Z0-9]+]] = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(3)* @l…
/external/v8/tools/
D	mingw-generate-makefiles.sh	`90 \| sed -e 's\|$[)a-zA-Z0-9]$\\$[a-zA-Z]$\|\1/\2\|g' \ 91 -e 's\|$[)a-zA-Z0-9]$\\\\$[a-zA-Z]$\|\1/\2\|g' \`
/external/llvm/test/CodeGen/XCore/
D	exception.ll	`43 ; CHECK-NEXT: [[START:.L[a-zA-Z0-9_]+]] 46 ; CHECK: .cfi_lsda 0, [[LSDA:.L[a-zA-Z0-9_]+]] 60 ; CHECK: [[PRE_G:.L[a-zA-Z0-9_]+]] 62 ; CHECK: [[POST_G:.L[a-zA-Z0-9_]+]] 63 ; CHECK: [[RETURN:.L[a-zA-Z0-9_]+]] 72 ; CHECK: {{.L[a-zA-Z0-9_]+}} 73 ; CHECK: [[LANDING:.L[a-zA-Z0-9_]+]] 95 ; CHECK: [[END:.L[a-zA-Z0-9_]+]]`
/external/llvm/utils/vim/syntax/
D	llvm.vim	`74 syn match llvmLabel /[-a-zA-Z$._][-a-zA-Z$._0-9]:/ 75 syn match llvmIdentifier /[%@][-a-zA-Z$._][-a-zA-Z$._0-9]/ 78 syn match llvmIdentifier /![-a-zA-Z$._][-a-zA-Z$._0-9]\ze\s$/ 79 syn match llvmIdentifier /![-a-zA-Z$._][-a-zA-Z$._0-9]\ze\s[=!]/ 82 syn match llvmConstant /\<DW_ATE_[a-zA-Z_]\+\>/ 83 syn match llvmConstant /\<DW_OP_[a-zA-Z0-9_]\+\>/ 84 syn match llvmConstant /\<DW_LANG_[a-zA-Z0-9_]\+\>/`
/external/mdnsresponder/mDNSShared/
D	dnsextd_lexer.l	`78 [a-zA-Z0-9]+(\.[a-zA-Z0-9]+)* yylval.string = strdup(yytext); return HOSTNAME; 79 [a-zA-Z0-9\.]+([a-zA-Z0-9\.]+)* yylval.string = strdup(yytext); return DOMAINNAME;`
/external/neven/Embedded/common/src/b_TensorEm/
D	Flt16Vec3D.c	169 struct bts_Flt16Vec3D bts_Flt16Vec3D_create16( int16 xA, int16 yA, int16 zA, int16 bbpA ) in bts_Flt16Vec3D_create16() argument 174 vecL.zE = zA; in bts_Flt16Vec3D_create16() 181 struct bts_Flt16Vec3D bts_Flt16Vec3D_create32( int32 xA, int32 yA, int32 zA, int32 bbpA ) in bts_Flt16Vec3D_create32() argument 184 if( ( xA \| yA \| zA ) == 0 ) in bts_Flt16Vec3D_create32() 193 int32 shiftL = bts_maxAbsIntLog2Of3( xA, yA, zA ) - 13; in bts_Flt16Vec3D_create32() 200 vecL.zE = ( ( zA >> sh1L ) + 1 ) >> 1; in bts_Flt16Vec3D_create32() 206 vecL.zE = zA << -shiftL; in bts_Flt16Vec3D_create32()
/external/llvm/test/Transforms/StructurizeCFG/
D	loop-multiple-exits.ll	`29 ; CHECK: br i1 %{{[0-9a-zA-Z_]+}}, label %for.inc, label %[[FLOW1:[0-9a-zA-Z_]+]] 32 ; CHECK: [[FLOW:[0-9a-zA-Z]+]]: 33 ; CHECK: br i1 %{{[0-9a-zA-Z_]+}}, label %for.end, label %for.cond`
/external/elfutils/libcpu/
D	i386_lex.l	`45 ID [a-zA-Z_][a-zA-Z0-9_/]* 46 ID2 [a-zA-Z0-9_:/]*`

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