/external/llvm/test/MC/AArch64/ |
D | neon-perm.s | 89 zip2 v0.8b, v1.8b, v2.8b 90 zip2 v0.16b, v1.16b, v2.16b 91 zip2 v0.4h, v1.4h, v2.4h 92 zip2 v0.8h, v1.8h, v2.8h 93 zip2 v0.2s, v1.2s, v2.2s 94 zip2 v0.4s, v1.4s, v2.4s 95 zip2 v0.2d, v1.2d, v2.2d
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D | neon-diagnostics.s | 6562 zip2 v0.16b, v1.8b, v2.8b 6563 zip2 v0.8b, v1.4b, v2.4b 6564 zip2 v0.8h, v1.4h, v2.4h 6565 zip2 v0.4h, v1.2h, v2.2h 6566 zip2 v0.4s, v1.2s, v2.2s 6567 zip2 v0.2s, v1.1s, v2.1s 6568 zip2 v0.2d, v1.1d, v2.1d 6569 zip2 v0.1d, v1.1d, v2.1d 6770 zip2 v0.16b, v1.8b, v2.8b 6771 zip2 v0.8b, v1.4b, v2.4b [all …]
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-zip.ll | 6 ;CHECK: zip2.8b 19 ;CHECK: zip2.4h 32 ;CHECK: zip2.16b 45 ;CHECK: zip2.8h 58 ;CHECK: zip2.4s 71 ;CHECK: zip2.4s 86 ;CHECK: zip2.8b 99 ;CHECK: zip2.16b
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D | neon-perm.ll | 224 ; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 240 ; CHECK: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 280 ; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 296 ; CHECK: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 304 ; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 320 ; CHECK: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 528 ; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 536 ; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 544 ; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 552 ; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h [all …]
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D | arm64-trn.ll | 33 ;CHECK: zip2.2s 46 ;CHECK: zip2.2s
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/external/libhevc/common/arm64/ |
D | ihevc_inter_pred_filters_luma_horz.s | 517 …zip2 v12.2s, v20.2s, v22.2s //vector zip the i iteration and ii interation in single r… 519 zip2 v13.2s, v21.2s, v23.2s 527 zip2 v14.2s, v20.2s, v22.2s 529 zip2 v15.2s, v21.2s, v23.2s 537 zip2 v16.2s, v20.2s, v22.2s 539 zip2 v17.2s, v21.2s, v23.2s 547 zip2 v18.2s, v20.2s, v22.2s 549 zip2 v19.2s, v21.2s, v23.2s
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D | ihevc_inter_pred_luma_horz_w16out.s | 217 …zip2 v12.2s, v20.2s, v22.2s //vector zip the i iteration and ii interation in single r… 219 zip2 v13.2s, v21.2s, v23.2s 227 zip2 v14.2s, v20.2s, v22.2s 229 zip2 v15.2s, v21.2s, v23.2s 237 zip2 v16.2s, v20.2s, v22.2s 239 zip2 v17.2s, v21.2s, v23.2s 272 zip2 v18.2s, v20.2s, v22.2s 274 zip2 v19.2s, v21.2s, v23.2s
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D | ihevc_intra_pred_chroma_mode2.s | 273 zip2 v1.8b, v0.8b, v1.8b 282 zip2 v3.8b, v2.8b, v3.8b 292 zip2 v5.8b, v4.8b, v5.8b 299 zip2 v7.8b, v6.8b, v7.8b
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D | ihevc_intra_pred_chroma_planar.s | 175 zip2 v25.8b, v17.8b, v25.8b 329 zip2 v25.8b, v17.8b, v25.8b 343 zip2 v25.8b, v17.8b, v25.8b
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D | ihevc_inter_pred_chroma_horz.s | 735 …zip2 v4.2s, v20.2s, v16.2s //vector zip the i iteration and ii interation in single r… 737 zip2 v5.2s, v21.2s, v17.2s 739 zip2 v6.2s, v22.2s, v18.2s 741 zip2 v7.2s, v23.2s, v19.2s
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D | ihevc_inter_pred_chroma_horz_w16out.s | 717 …zip2 v4.2s, v20.2s, v16.2s //vector zip the i iteration and ii interation in single r… 719 zip2 v5.2s, v21.2s, v17.2s 721 zip2 v6.2s, v22.2s, v18.2s 723 zip2 v7.2s, v23.2s, v19.2s
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/external/libavc/common/armv8/ |
D | ih264_intra_pred_chroma_av8.s | 479 zip2 v24.8h, v4.8h, v24.8h 482 zip2 v26.8h, v6.8h, v26.8h 485 zip2 v2.8h, v0.8h, v2.8h 496 zip2 v10.8h, v8.8h, v10.8h
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D | ih264_deblk_chroma_av8.s | 526 zip2 v13.8b, v12.8b, v13.8b
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | neon-instructions.txt | 2265 # CHECK: zip2 v4.8b, v3.8b, v2.8b 2266 # CHECK: zip2 v21.16b, v2.16b, v2.16b 2267 # CHECK: zip2 v6.4h, v2.4h, v2.4h 2268 # CHECK: zip2 v23.8h, v1.8h, v2.8h 2269 # CHECK: zip2 v8.2s, v1.2s, v2.2s 2270 # CHECK: zip2 v25.4s, v0.4s, v2.4s 2271 # CHECK: zip2 v10.2d, v0.2d, v2.2d
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/external/vixl/src/vixl/a64/ |
D | simulator-a64.h | 1944 LogicVRegister zip2(VectorFormat vform,
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D | macro-assembler-a64.h | 2237 V(zip2, Zip2)
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D | assembler-a64.h | 3252 void zip2(const VRegister& vd,
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D | simulator-a64.cc | 3862 case NEON_ZIP2: zip2(vf, rd, rn, rm); break; in VisitNEONPerm()
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D | logic-a64.cc | 3455 LogicVRegister Simulator::zip2(VectorFormat vform, in zip2() function in vixl::Simulator
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D | assembler-a64.cc | 4129 void Assembler::zip2(const VRegister& vd, in zip2() function in vixl::Assembler
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/external/valgrind/none/tests/arm64/ |
D | fp_and_simd.stdout.exp | 28783 zip2 v1.2d, v2.2d, v4.2d 1b11d27123898355aa3dcd69d32652be 3782b6e100d5d5bfa58c471a19973a28 24… 28784 zip2 v1.4s, v2.4s, v4.4s 851b3a94ad2efe0c54f8b14464dce1eb b1582aebae70823c0288ee6bc5dde32e a0… 28785 zip2 v1.2s, v2.2s, v4.2s a2232dafe077ca2ed9ccc9e6eb7a9684 23bd0c06b229e2029633628c20cca512 20… 28786 zip2 v1.8h, v2.8h, v4.8h 932df5a65e035b58b51c71f6f04400a7 7ed3687bb6f34d70da484ed7eff69f5d 1f… 28787 zip2 v1.4h, v2.4h, v4.4h 5bcff5eeea27d7bf6ffc8d68b90ec008 c72ea2bf7e23eab84fdb9542782d77c4 a2… 28788 zip2 v1.16b, v2.16b, v4.16b 02621d45ce0cda0f7c001ac0fe48d1fa ad65c201cd4e6189ed69fd06cfb7153c 5… 28789 zip2 v1.8b, v2.8b, v4.8b 33033f816b0243a8e2cbc246c5194fb5 43193aaa3b1a3664551f4cd64b9f583e 4e…
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/external/vixl/test/ |
D | test-simulator-a64.cc | 4057 DEFINE_TEST_NEON_3SAME(zip2, Basic)
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/external/vixl/doc/ |
D | supported-instructions.md | 4654 void zip2(const VRegister& vd,
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.td | 3622 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
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