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Searched refs:REG_MSVDX_VEC_IQRAM_OFFSET (Results 1 – 8 of 8) sorted by relevance

/hardware/intel/img/psb_video/src/hwdefs/
Dmsvdx_defs.h61 #define REG_MSVDX_VEC_IQRAM_OFFSET 0x00000700 macro
/hardware/intel/img/psb_video/src/
Dtng_jpegdec.c616 psb_cmdbuf_rendec_start(cmdbuf, REG_MSVDX_VEC_IQRAM_OFFSET); in tng__JPEG_write_qmatrices()
Dpnw_MPEG2.c1181 psb_cmdbuf_rendec_start(cmdbuf, REG_MSVDX_VEC_IQRAM_OFFSET); in psb__MPEG2_write_qmatrices()
Dpnw_MPEG4.c1657 psb_cmdbuf_rendec_start(cmdbuf, REG_MSVDX_VEC_IQRAM_OFFSET); in psb__MPEG4_write_qmatrices()
Dpnw_H264.c969 psb_cmdbuf_rendec_start(cmdbuf, REG_MSVDX_VEC_IQRAM_OFFSET); in psb__H264_build_SCA_chunk()
/hardware/intel/img/psb_video/src/mrst/
Dpsb_MPEG2.c1203 psb_cmdbuf_rendec_start_chunk(cmdbuf, REG_MSVDX_VEC_IQRAM_OFFSET); in psb__MPEG2_write_qmatrices()
Dpsb_H264.c831 psb_cmdbuf_rendec_start_chunk(cmdbuf, REG_MSVDX_VEC_IQRAM_OFFSET); in psb__H264_build_SCA_chunk()
Dpsb_MPEG4.c836 psb_cmdbuf_rendec_start_chunk(cmdbuf, REG_MSVDX_VEC_IQRAM_OFFSET); in psb__MPEG4_write_qmatrices()