Searched refs:SPI (Results 1 – 16 of 16) sorted by relevance
| /hardware/bsp/intel/peripheral/libmraa/docs/ |
| D | raspberry_pi.md | 47 | 19 | P1-19 | SPI MOSI |
49 | 21 | P1-21 | SPI MISO |
51 | 23 | P1-23 | SPI SCL |
52 | 24 | P1-24 | SPI CS0 |
54 | 26 | P1-26 | SPI CS1 |
79 | 19 | P1-19 | SPI MOSI |
81 | 21 | P1-21 | SPI MISO |
83 | 23 | P1-23 | SPI SCL |
84 | 24 | P1-24 | SPI CS0 |
86 | 26 | P1-26 | SPI CS1 |
[all …]
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| D | minnow_max.md | 15 SPI section in Intel(R) Minnowboard Max {#minnowmax}
17 For SPI support you need to load the low_speed_spidev kernel module and that
18 will create the /dev/spidev0.0 device node. Mraa only knows about this one SPI
37 | 5 | 5 | SPI_CS | 220 | SPI (via low_speed) |
39 | 7 | 7 | SPI_MISO | 221 | SPI (via low_speed) |
41 | 9 | 9 | SPI_MOSI | 222 | SPI (via low_speed) |
43 | 11 | 11 | SPI_CLK | 223 | SPI (via low_speed) |
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| D | banana_pi.md | 28 **SPI** works fine when used with old 3.4 Kernels provided by Lemaker, on
29 Mainline Kernel SPI does currently not work
67 | 19 | P1-19 | SPI MOSI |
69 | 21 | P1-21 | SPI MISO |
71 | 23 | P1-23 | SPI SCL |
72 | 24 | P1-24 | SPI CS0 |
74 | 26 | P1-26 | SPI CS1 |
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| D | edison.md | 22 - SPI exposed is also used for the ADC. Try not to use your own CS.
23 - Max SPI speed is 25Mhz/4 ~6.25Mhz
24 - SPI PM can sometimes do weird things you can disable it with:
64 | 9 | J17-10 | GP111 | | GPIO-111 | SPI-5-CS1 | …
65 | 10 | J17-11 | GP109 | | GPIO-109 | SPI-5-SCK | …
66 | 11 | J17-12 | GP115 | | GPIO-115 | SPI-5-MOSI | …
78 | 23 | J18-10 | GP110 | | GPIO-110 | SPI-5-CS0 | …
79 | 24 | J18-11 | GP114 | | GPIO-114 | SPI-5-MISO | …
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| D | changelog.md | 18 * Nodejs SPI tweaks
41 * Fix SPI CS pin caps causing mux_total to be > 0
84 * SPI add CS exposure
124 * prefix SPI mode with MRAA_SPI_
128 * SPI Mode function now functional, API Change in SPI
178 * SPI, implementation completed.
198 * Initial SPI implementation is provided
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| D | ftdi_ft4222.md | 4 The FT4222H is a High/Full Speed USB2.0-to-Quad SPI/I2C device controller. Mraa
13 CNFMODE0 the chip can provide either 4 GPIOs and SPI, or 2 GPIOs and I2C
16 CNFMODE3 on the other hand will only provide SPI or I2C.
63 are still under development (e.g. SPI replacement functions).
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| D | beaglebone.md | 31 **SPI** works fine with 3.8.13 kernels, on Mainline Kernel SPI does currently
44 It will also tell you which overlay for SPI/COM/I2C/PWM it tries to load, on
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| /hardware/intel/bootstub/ |
| D | bootstub.spec | 38 - add SPI controller selection flag
45 - add SPI uart suppression flag
47 - change SPI uart slave select to 0x2 according to ESL 2008.06 version
49 - add SPI uart support
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| D | VERSION | 6 0.7 build e820 table and add SPI controller selection. June 4, 2009
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| /hardware/bsp/intel/peripheral/libupm/src/st7735/ |
| D | CMakeLists.txt | 2 set (libdescription "libupm SPI LCD")
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| /hardware/bsp/intel/peripheral/libmraa/src/javascript/ |
| D | package.json.cmake | 3 …"description": "IO library that helps you use I2c, SPI, gpio, uart, pwm, analog inputs (aio) and m…
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| /hardware/bsp/intel/peripheral/libupm/docs/ |
| D | knownlimitations.md | 51 Edison SPI bus limitation. Sensor works as expected with the Intel Galileo
54 on Intel Edison boards also due to SPI bus limitation and data corruption.
66 The Intel Edison *SPI* bus can corrupt data being sent across when certain
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| D | max31855.md | 50 In the adafruit library the read function (our chip is a 3pin SPI so only read
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| /hardware/bsp/intel/peripheral/libupm/src/wt5001/ |
| D | wt5001.h | 118 SPI, enumerator
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| D | wt5001.cxx | 203 case SPI: in play()
490 case SPI: in getNumFiles()
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| /hardware/bsp/intel/peripheral/libmraa/src/python/docs/ |
| D | example.rst | 66 The ADC is typically provided on a dedicated or shared SPI bus, this is
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