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Searched refs:v7 (Results 1 – 12 of 12) sorted by relevance

/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/ppc/
Dsad_altivec.asm48 vsububs v7, v5, v4
49 vor v6, v6, v7
72 vsububs v7, v5, v4
80 vor v6, v6, v7
94 vsububs v7, v5, v9
96 vor v6, v6, v7
104 vspltisw v7, 0
106 vsumsws v8, v8, v7
125 load_aligned_16 v7, r5, r10
132 vmrghb v5, v5, v7
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Didctllm_altivec.asm43 vsubsws v7, v2, v3 ;# b1 = ip[0]-ip[8]
70 vaddsws v1, v7, v4 ;# b1 + c1
71 vsubsws v2, v7, v4 ;# b1 - c1
78 vmrglw v7, v2, v3 ;# c2 d2 c3 d3
83 vperm v2, v6, v7, v10 ;# a2 b2 c2 d2
84 vperm v3, v6, v7, v11 ;# a3 b3 c3 d3
88 vsubsws v7, v0, v2 ;# b1 = ip[0]-ip[8]
113 vaddsws v1, v7, v4 ;# b1 + c1
114 vsubsws v2, v7, v4 ;# b1 - c1
117 vspltish v7, 3
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Dvariance_altivec.asm39 vspltisw v7, 0 ;# zero for merging
54 vmrghb v2, v7, v4
55 vmrghb v3, v7, v5
59 vmrglb v2, v7, v4
60 vmrglb v3, v7, v5
86 vsumsws v8, v8, v7
87 vsumsws v9, v9, v7
130 vsumsws v8, v8, v7
131 vsumsws v9, v9, v7
223 vsumsws v9, v9, v7
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Dloopfilter_filters_altivec.asm123 Tpair v30,v31, v7,v15
130 Tpair v6,v7, v19,v27
178 ;# It acts in place on registers v0...v3, uses v4...v7 as temporaries,
190 vmrglb v7, v2, v3
196 vmrghh v2, v5, v7
197 vmrglh v3, v5, v7
204 vmrglw v7, v2, v3
210 vperm v2, v5, v7, \Vlo
211 vperm v3, v5, v7, \Vhi
244 ;# The input/output is in registers v0...v7. We use v10...v17 as mirrors;
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Dfilter_altivec.asm81 vsrh v16, v16, v7 ;# divide by 128
82 vsrh v17, v17, v7 ;# v16 v17 = evens, odds
448 Read8x8 v7, r3, r4, 1
454 interp_8x8 v7
473 Read8x8 v7, r3, r4, 1
494 vinterp_no_store_8x8 v2, v3, v4, v5, v6, v7
495 vinterp_no_store_8x8 v3, v4, v5, v6, v7, v8
943 vspltish v7, 7
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/encoder/ppc/
Dfdct_altivec.asm66 vsraw v10, v10, v7 ;# v10 = A0 A1 B0 B1
70 vsraw v11, v11, v7 ;# v11 = A2 A3 B2 B3
84 vsraw v10, v8, v7
90 vsraw v8, v8, v7
115 vspltisw v7, 14 ;# == 14, fits in 5 signed bits
126 vspltisw v7, -16 ;# == 16 == -16, only low 5 bits matter
144 vspltisw v7, 14 ;# == 14, fits in 5 signed bits
155 vspltisw v7, -16 ;# == 16 == -16, only low 5 bits matter
167 vspltisw v7, 14 ;# == 14, fits in 5 signed bits
177 vspltisw v7, -16 ;# == 16 == -16, only low 5 bits matter
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/encoder/x86/
Dvp9_dct_avx2.c357 const __m128i v7 = _mm_add_epi32(u7, k__DCT_CONST_ROUNDING); in vp9_fdct8x8_avx2() local
365 const __m128i w7 = _mm_srai_epi32(v7, DCT_CONST_BITS); in vp9_fdct8x8_avx2()
419 const __m128i v7 = _mm_add_epi32(u7, k__DCT_CONST_ROUNDING); in vp9_fdct8x8_avx2() local
427 const __m128i w7 = _mm_srai_epi32(v7, DCT_CONST_BITS); in vp9_fdct8x8_avx2()
677 __m128i v0, v1, v2, v3, v4, v5, v6, v7; in fdct8_avx2() local
717 v7 = _mm_add_epi32(u7, k__DCT_CONST_ROUNDING); in fdct8_avx2()
726 u7 = _mm_srai_epi32(v7, DCT_CONST_BITS); in fdct8_avx2()
775 v7 = _mm_madd_epi16(u1, k__cospi_m04_p28); in fdct8_avx2()
785 u7 = _mm_add_epi32(v7, k__DCT_CONST_ROUNDING); in fdct8_avx2()
794 v7 = _mm_srai_epi32(u7, DCT_CONST_BITS); in fdct8_avx2()
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Dvp9_dct_sse2.c458 const __m128i v7 = _mm_add_epi32(u7, k__DCT_CONST_ROUNDING); in vp9_fdct8x8_sse2() local
466 const __m128i w7 = _mm_srai_epi32(v7, DCT_CONST_BITS); in vp9_fdct8x8_sse2()
520 const __m128i v7 = _mm_add_epi32(u7, k__DCT_CONST_ROUNDING); in vp9_fdct8x8_sse2() local
528 const __m128i w7 = _mm_srai_epi32(v7, DCT_CONST_BITS); in vp9_fdct8x8_sse2()
778 __m128i v0, v1, v2, v3, v4, v5, v6, v7; in fdct8_sse2() local
818 v7 = _mm_add_epi32(u7, k__DCT_CONST_ROUNDING); in fdct8_sse2()
827 u7 = _mm_srai_epi32(v7, DCT_CONST_BITS); in fdct8_sse2()
876 v7 = _mm_madd_epi16(u1, k__cospi_m04_p28); in fdct8_sse2()
886 u7 = _mm_add_epi32(v7, k__DCT_CONST_ROUNDING); in fdct8_sse2()
895 v7 = _mm_srai_epi32(u7, DCT_CONST_BITS); in fdct8_sse2()
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/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/third_party/googletest/src/include/gtest/
Dgtest.h10825 ValueArray7(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7) : v1_(v1),
10826 v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7) {}
10853 ValueArray8(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7,
10854 T8 v8) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7),
10883 ValueArray9(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8,
10884 T9 v9) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7),
10915 ValueArray10(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9,
10916 T10 v10) : v1_(v1), v2_(v2), v3_(v3), v4_(v4), v5_(v5), v6_(v6), v7_(v7),
10949 ValueArray11(T1 v1, T2 v2, T3 v3, T4 v4, T5 v5, T6 v6, T7 v7, T8 v8, T9 v9,
10951 v7_(v7), v8_(v8), v9_(v9), v10_(v10), v11_(v11) {}
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/hardware/bsp/intel/peripheral/libupm/cmake/modules/
DTargetArch.cmake3 # Currently handles arm (v5, v6, v7), x86 (32/64), ia64, and ppc (32/64)
/hardware/bsp/intel/peripheral/libmraa/cmake/modules/
DTargetArch.cmake3 # Currently handles arm (v5, v6, v7), x86 (32/64), ia64, and ppc (32/64)
/hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/x86/
Dvp9_idct_intrin_sse2.c720 __m128i v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15; in iadst8_sse2() local
793 v7 = _mm_add_epi32(w7, k__DCT_CONST_ROUNDING); in iadst8_sse2()
810 u7 = _mm_srai_epi32(v7, DCT_CONST_BITS); in iadst8_sse2()
847 v7 = _mm_madd_epi16(u3, k__cospi_p08_p24); in iadst8_sse2()
852 w3 = _mm_add_epi32(v3, v7); in iadst8_sse2()
856 w7 = _mm_sub_epi32(v3, v7); in iadst8_sse2()
865 v7 = _mm_add_epi32(w7, k__DCT_CONST_ROUNDING); in iadst8_sse2()
874 u7 = _mm_srai_epi32(v7, DCT_CONST_BITS); in iadst8_sse2()
895 v7 = _mm_madd_epi16(u3, k__cospi_p16_m16); in iadst8_sse2()
904 u7 = _mm_add_epi32(v7, k__DCT_CONST_ROUNDING); in iadst8_sse2()
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