/system/core/libpixelflinger/codeflinger/ |
D | ARMAssembler.cpp | 229 int Rd, int Rm, int Rs, int Rn) { in MLA() argument 230 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; } in MLA() 231 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn); in MLA() 233 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm; in MLA() 236 int Rd, int Rm, int Rs) { in MUL() argument 237 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; } in MUL() 238 LOG_FATAL_IF(Rd==Rm, "MUL(r%u,r%u,r%u)", Rd,Rm,Rs); in MUL() 239 *mPC++ = (cc<<28) | (s<<20) | (Rd<<16) | (Rs<<8) | 0x90 | Rm; in MUL() 242 int RdLo, int RdHi, int Rm, int Rs) { in UMULL() argument 243 LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi, in UMULL() [all …]
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D | ARMAssemblerProxy.cpp | 93 uint32_t ARMAssemblerProxy::reg_imm(int Rm, int type, uint32_t shift) in reg_imm() argument 95 return mTarget->reg_imm(Rm, type, shift); in reg_imm() 98 uint32_t ARMAssemblerProxy::reg_rrx(int Rm) in reg_rrx() argument 100 return mTarget->reg_rrx(Rm); in reg_rrx() 103 uint32_t ARMAssemblerProxy::reg_reg(int Rm, int type, int Rs) in reg_reg() argument 105 return mTarget->reg_reg(Rm, type, Rs); in reg_reg() 122 uint32_t ARMAssemblerProxy::reg_scale_pre(int Rm, int type, uint32_t shift, int W) in reg_scale_pre() argument 124 return mTarget->reg_scale_pre(Rm, type, shift, W); in reg_scale_pre() 127 uint32_t ARMAssemblerProxy::reg_scale_post(int Rm, int type, uint32_t shift) in reg_scale_post() argument 129 return mTarget->reg_scale_post(Rm, type, shift); in reg_scale_post() [all …]
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D | ARMAssemblerInterface.h | 81 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift) = 0; 82 virtual uint32_t reg_rrx(int Rm) = 0; 83 virtual uint32_t reg_reg(int Rm, int type, int Rs) = 0; 90 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0) = 0; 91 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0) = 0; 97 virtual uint32_t reg_pre(int Rm, int W=0) = 0; 98 virtual uint32_t reg_post(int Rm) = 0; 129 int Rd, int Rm, int Rs, int Rn) = 0; 131 int Rd, int Rm, int Rs) = 0; 133 int RdLo, int RdHi, int Rm, int Rs) = 0; [all …]
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D | ARMAssemblerProxy.h | 59 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift); 60 virtual uint32_t reg_rrx(int Rm); 61 virtual uint32_t reg_reg(int Rm, int type, int Rs); 68 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0); 69 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0); 75 virtual uint32_t reg_pre(int Rm, int W=0); 76 virtual uint32_t reg_post(int Rm); 83 int Rd, int Rm, int Rs, int Rn); 85 int Rd, int Rm, int Rs); 87 int RdLo, int RdHi, int Rm, int Rs); [all …]
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D | ARMAssembler.h | 70 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift); 71 virtual uint32_t reg_rrx(int Rm); 72 virtual uint32_t reg_reg(int Rm, int type, int Rs); 79 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0); 80 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0); 86 virtual uint32_t reg_pre(int Rm, int W=0); 87 virtual uint32_t reg_post(int Rm); 94 int Rd, int Rm, int Rs, int Rn); 96 int Rd, int Rm, int Rs); 98 int RdLo, int RdHi, int Rm, int Rs); [all …]
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D | Arm64Assembler.h | 83 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift); 84 virtual uint32_t reg_rrx(int Rm); 85 virtual uint32_t reg_reg(int Rm, int type, int Rs); 90 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0); 91 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0); 94 virtual uint32_t reg_pre(int Rm, int W=0); 95 virtual uint32_t reg_post(int Rm); 102 int Rd, int Rm, int Rs, int Rn); 104 int Rd, int Rm, int Rs); 106 int RdLo, int RdHi, int Rm, int Rs); [all …]
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D | Arm64Assembler.cpp | 376 uint32_t Rm; in dataProcessingCommon() local 382 Rm = mAddrMode.reg_imm_Rm; in dataProcessingCommon() 388 Rm = Op2; in dataProcessingCommon() 398 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break; in dataProcessingCommon() 399 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break; in dataProcessingCommon() 400 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break; in dataProcessingCommon() 401 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break; in dataProcessingCommon() 402 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break; in dataProcessingCommon() 472 int Rm = mAddrMode.reg_imm_Rm; in ADDR_ADD() local 474 *mPC++ = A64_ADD_X_Wm_SXTW(Rd, Rn, Rm, amount); in ADDR_ADD() [all …]
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D | MIPS64Assembler.h | 73 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift); 74 virtual uint32_t reg_rrx(int Rm); 75 virtual uint32_t reg_reg(int Rm, int type, int Rs); 82 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0); 83 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0); 89 virtual uint32_t reg_pre(int Rm, int W=0); 90 virtual uint32_t reg_post(int Rm); 99 int Rd, int Rm, int Rs, int Rn); 101 int Rd, int Rm, int Rs); 103 int RdLo, int RdHi, int Rm, int Rs); [all …]
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D | MIPSAssembler.h | 68 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift); 69 virtual uint32_t reg_rrx(int Rm); 70 virtual uint32_t reg_reg(int Rm, int type, int Rs); 77 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0); 78 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0); 84 virtual uint32_t reg_pre(int Rm, int W=0); 85 virtual uint32_t reg_post(int Rm); 94 int Rd, int Rm, int Rs, int Rn); 96 int Rd, int Rm, int Rs); 98 int RdLo, int RdHi, int Rm, int Rs); [all …]
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D | MIPS64Assembler.cpp | 227 uint32_t ArmToMips64Assembler::reg_imm(int Rm, int type, uint32_t shift) in reg_imm() argument 229 amode.reg = Rm; in reg_imm() 235 uint32_t ArmToMips64Assembler::reg_rrx(int Rm) in reg_rrx() argument 241 uint32_t ArmToMips64Assembler::reg_reg(int Rm, int type, int Rs) in reg_reg() argument 270 uint32_t ArmToMips64Assembler::reg_scale_pre(int Rm, int type, in reg_scale_pre() argument 275 amode.reg = Rm; in reg_scale_pre() 282 uint32_t ArmToMips64Assembler::reg_scale_post(int Rm, int type, uint32_t shift) in reg_scale_post() argument 308 uint32_t ArmToMips64Assembler::reg_pre(int Rm, int W) in reg_pre() argument 311 amode.reg = Rm; in reg_pre() 315 uint32_t ArmToMips64Assembler::reg_post(int Rm) in reg_post() argument [all …]
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D | MIPSAssembler.cpp | 234 uint32_t ArmToMipsAssembler::reg_imm(int Rm, int type, uint32_t shift) in reg_imm() argument 236 amode.reg = Rm; in reg_imm() 242 uint32_t ArmToMipsAssembler::reg_rrx(int Rm) in reg_rrx() argument 248 uint32_t ArmToMipsAssembler::reg_reg(int Rm, int type, int Rs) in reg_reg() argument 277 uint32_t ArmToMipsAssembler::reg_scale_pre(int Rm, int type, in reg_scale_pre() argument 282 amode.reg = Rm; in reg_scale_pre() 289 uint32_t ArmToMipsAssembler::reg_scale_post(int Rm, int type, uint32_t shift) in reg_scale_post() argument 319 uint32_t ArmToMipsAssembler::reg_pre(int Rm, int W) in reg_pre() argument 322 amode.reg = Rm; in reg_pre() 326 uint32_t ArmToMipsAssembler::reg_post(int Rm) in reg_post() argument [all …]
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/system/core/libpixelflinger/tests/arch-arm64/assembler/ |
D | arm64_assembler_test.cpp | 415 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3) in dataOpTest() argument 440 op2 = Rm; in dataOpTest() 441 regs[Rm] = test.RmValue; in dataOpTest() 445 op2 = a64asm->reg_imm(Rm, test.shiftMode, test.shiftAmount); in dataOpTest() 446 regs[Rm] = test.RmValue; in dataOpTest() 456 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break; in dataOpTest() 457 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break; in dataOpTest() 461 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break; in dataOpTest() 462 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break; in dataOpTest() 463 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,Rs); break; in dataOpTest() [all …]
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/system/core/libpixelflinger/tests/arch-mips64/assembler/ |
D | mips64_assembler_test.cpp | 373 uint32_t Rn = R_t0, uint32_t Rm = R_t1, uint32_t Rs = R_t2) in dataOpTest() argument 402 op2 = Rm; in dataOpTest() 403 regs[Rm] = (int64_t)((int32_t)(test.RmValue)); in dataOpTest() 407 op2 = a64asm->reg_imm(Rm, test.shiftMode, test.shiftAmount); in dataOpTest() 408 regs[Rm] = (int64_t)((int32_t)(test.RmValue)); in dataOpTest() 418 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break; in dataOpTest() 419 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break; in dataOpTest() 423 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break; in dataOpTest() 424 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break; in dataOpTest() 425 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,Rs); break; in dataOpTest() [all …]
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