| /system/core/libpixelflinger/codeflinger/ |
| D | MIPSAssembler.h | 273 void ADDU(int Rd, int Rs, int Rt);
274 void ADDIU(int Rt, int Rs, int16_t imm);
275 void SUBU(int Rd, int Rs, int Rt);
276 void SUBIU(int Rt, int Rs, int16_t imm);
278 void MUL(int Rd, int Rs, int Rt);
279 void MULT(int Rs, int Rt); // dest is hi,lo
280 void MULTU(int Rs, int Rt); // dest is hi,lo
281 void MADD(int Rs, int Rt); // hi,lo = hi,lo + Rs * Rt
282 void MADDU(int Rs, int Rt); // hi,lo = hi,lo + Rs * Rt
283 void MSUB(int Rs, int Rt); // hi,lo = hi,lo - Rs * Rt
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| D | MIPSAssembler.cpp | 1445 void MIPSAssembler::ADDU(int Rd, int Rs, int Rt) in ADDU() argument
1448 | (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF); in ADDU()
1452 void MIPSAssembler::ADDIU(int Rt, int Rs, int16_t imm) in ADDIU() argument
1454 *mPC++ = (addiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16); in ADDIU()
1458 void MIPSAssembler::SUBU(int Rd, int Rs, int Rt) in SUBU() argument
1461 (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF) ; in SUBU()
1465 void MIPSAssembler::SUBIU(int Rt, int Rs, int16_t imm) // really addiu(d, s, -j) in SUBIU() argument
1467 *mPC++ = (addiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | ((-imm) & MSK_16); in SUBIU()
1476 void MIPSAssembler::MUL(int Rd, int Rs, int Rt) in MUL() argument
1479 (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF) ; in MUL()
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| D | MIPS64Assembler.h | 273 void DADDU(int Rd, int Rs, int Rt);
274 void DADDIU(int Rt, int Rs, int16_t imm);
275 void DSUBU(int Rd, int Rs, int Rt);
276 void DSUBIU(int Rt, int Rs, int16_t imm);
277 virtual void MUL(int Rd, int Rs, int Rt);
278 void MUH(int Rd, int Rs, int Rt);
293 void LD(int Rt, int Rbase, int16_t offset);
294 void SD(int Rt, int Rbase, int16_t offset);
295 virtual void LUI(int Rt, int16_t offset);
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| D | MIPS64Assembler.cpp | 1383 void MIPS64Assembler::DADDU(int Rd, int Rs, int Rt) in DADDU() argument
1386 | (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF); in DADDU()
1389 void MIPS64Assembler::DADDIU(int Rt, int Rs, int16_t imm) in DADDIU() argument
1391 *mPC++ = (daddiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16); in DADDIU()
1394 void MIPS64Assembler::DSUBU(int Rd, int Rs, int Rt) in DSUBU() argument
1397 (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF) ; in DSUBU()
1400 void MIPS64Assembler::DSUBIU(int Rt, int Rs, int16_t imm) // really addiu(d, s, -j) in DSUBIU() argument
1402 *mPC++ = (daddiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | ((-imm) & MSK_16); in DSUBIU()
1405 void MIPS64Assembler::MUL(int Rd, int Rs, int Rt) in MUL() argument
1408 (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF) ; in MUL()
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| D | Arm64Assembler.cpp | 1003 uint32_t size, uint32_t Rt, in A64_LDRSTR_Wm_SXTW_0() argument
1009 dataTransferOpName[op], Rt, Rn, Rm); in A64_LDRSTR_Wm_SXTW_0()
1010 return(dataTransferOpCode[op] | (Rm << 16) | (Rn << 5) | Rt); in A64_LDRSTR_Wm_SXTW_0()
1015 dataTransferOpName[op], Rt, Rn, Rm); in A64_LDRSTR_Wm_SXTW_0()
1016 return(dataTransferOpCode[op] | (0x1<<30) | (Rm<<16) | (Rn<<5)|Rt); in A64_LDRSTR_Wm_SXTW_0()
1020 uint32_t ArmToArm64Assembler::A64_STR_IMM_PreIndex(uint32_t Rt, in A64_STR_IMM_PreIndex() argument
1024 LOG_INSTR("STR W%d, [SP, #%d]!\n", Rt, simm); in A64_STR_IMM_PreIndex()
1026 LOG_INSTR("STR W%d, [X%d, #%d]!\n", Rt, Rn, simm); in A64_STR_IMM_PreIndex()
1029 return (0xB8 << 24) | (imm9 << 12) | (0x3 << 10) | (Rn << 5) | Rt; in A64_STR_IMM_PreIndex()
1032 uint32_t ArmToArm64Assembler::A64_LDR_IMM_PostIndex(uint32_t Rt, in A64_LDR_IMM_PostIndex() argument
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| D | Arm64Assembler.h | 198 uint32_t size, uint32_t Rt,
201 uint32_t A64_STR_IMM_PreIndex(uint32_t Rt, uint32_t Rn, int32_t simm);
202 uint32_t A64_LDR_IMM_PostIndex(uint32_t Rt,uint32_t Rn, int32_t simm);
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