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/toolchain/binutils/binutils-2.25/opcodes/
Daarch64-asm.c64 const aarch64_inst *inst ATTRIBUTE_UNUSED) in aarch64_ins_regno()
75 aarch64_insn *code, const aarch64_inst *inst) in aarch64_ins_reglane() argument
78 insert_field (self->fields[0], code, info->reglane.regno, inst->opcode->mask); in aarch64_ins_reglane()
80 if (inst->opcode->iclass == asisdone || inst->opcode->iclass == asimdins) in aarch64_ins_reglane()
84 && inst->opcode->operands[0] == AARCH64_OPND_Ed) in aarch64_ins_reglane()
133 const aarch64_inst *inst ATTRIBUTE_UNUSED) in aarch64_ins_reglist()
147 const aarch64_inst *inst) in aarch64_ins_ldst_reglist() argument
151 unsigned num = get_opcode_dependent_value (inst->opcode); in aarch64_ins_ldst_reglist()
190 const aarch64_inst *inst) in aarch64_ins_ldst_reglist_r() argument
195 int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1; in aarch64_ins_ldst_reglist_r()
[all …]
Daarch64-dis.c204 get_expected_qualifier (const aarch64_inst *inst, int i) in get_expected_qualifier() argument
208 assert (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL); in get_expected_qualifier()
209 if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list, in get_expected_qualifier()
221 const aarch64_inst *inst ATTRIBUTE_UNUSED) in aarch64_ext_regno()
230 const aarch64_inst *inst ATTRIBUTE_UNUSED) in aarch64_ext_regno_pair()
234 info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1; in aarch64_ext_regno_pair()
242 const aarch64_inst *inst ATTRIBUTE_UNUSED) in aarch64_ext_regrt_sysins()
246 && (aarch64_get_operand_class (inst->operands[0].type) in aarch64_ext_regrt_sysins()
251 info->present = inst->operands[0].sysins_op->has_xt; in aarch64_ext_regrt_sysins()
260 const aarch64_inst *inst ATTRIBUTE_UNUSED) in aarch64_ext_reglane()
[all …]
Dmicroblaze-dis.c174 unsigned long inst; in read_insn_microblaze() local
185 inst = (ibytes[0] << 24) | (ibytes[1] << 16) | (ibytes[2] << 8) | ibytes[3]; in read_insn_microblaze()
187 inst = (ibytes[3] << 24) | (ibytes[2] << 16) | (ibytes[1] << 8) | ibytes[0]; in read_insn_microblaze()
193 if (op->bit_sequence == (inst & op->opcode_mask)) in read_insn_microblaze()
197 return inst; in read_insn_microblaze()
206 unsigned long inst, prev_inst; in print_insn_microblaze() local
216 inst = read_insn_microblaze (memaddr, info, &op); in print_insn_microblaze()
217 if (inst == 0) in print_insn_microblaze()
245 print_func (stream, ".short 0x%04x", (unsigned int) inst); in print_insn_microblaze()
253 print_func (stream, "\t%s, %s, %s", get_field_rd (inst), in print_insn_microblaze()
[all …]
Daarch64-asm-2.c350 aarch64_insn *code, const aarch64_inst *inst) in aarch64_insert_operand() argument
381 return aarch64_ins_regno (self, info, code, inst); in aarch64_insert_operand()
383 return aarch64_ins_reg_extended (self, info, code, inst); in aarch64_insert_operand()
385 return aarch64_ins_reg_shifted (self, info, code, inst); in aarch64_insert_operand()
387 return aarch64_ins_ft (self, info, code, inst); in aarch64_insert_operand()
391 return aarch64_ins_reglane (self, info, code, inst); in aarch64_insert_operand()
393 return aarch64_ins_reglist (self, info, code, inst); in aarch64_insert_operand()
395 return aarch64_ins_ldst_reglist (self, info, code, inst); in aarch64_insert_operand()
397 return aarch64_ins_ldst_reglist_r (self, info, code, inst); in aarch64_insert_operand()
399 return aarch64_ins_ldst_elemlist (self, info, code, inst); in aarch64_insert_operand()
[all …]
Dmcore-dis.c98 unsigned short inst; local
113 inst = (ibytes[0] << 8) | ibytes[1];
115 inst = (ibytes[1] << 8) | ibytes[0];
121 if (op->inst == (inst & imsk[op->opclass]))
125 (*print_func) (stream, ".short 0x%04x", inst);
128 const char *name = grname[inst & 0x0F];
138 (*print_func) (stream, "\t%d", inst & 0x3);
148 (*print_func) (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]);
157 (*print_func) (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]);
165 (*print_func) (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1);
[all …]
Daarch64-dis-2.c8950 aarch64_insn code, const aarch64_inst *inst) in aarch64_extract_operand() argument
8980 return aarch64_ext_regno (self, info, code, inst); in aarch64_extract_operand()
8982 return aarch64_ext_regrt_sysins (self, info, code, inst); in aarch64_extract_operand()
8984 return aarch64_ext_regno_pair (self, info, code, inst); in aarch64_extract_operand()
8986 return aarch64_ext_reg_extended (self, info, code, inst); in aarch64_extract_operand()
8988 return aarch64_ext_reg_shifted (self, info, code, inst); in aarch64_extract_operand()
8990 return aarch64_ext_ft (self, info, code, inst); in aarch64_extract_operand()
8994 return aarch64_ext_reglane (self, info, code, inst); in aarch64_extract_operand()
8996 return aarch64_ext_reglist (self, info, code, inst); in aarch64_extract_operand()
8998 return aarch64_ext_ldst_reglist (self, info, code, inst); in aarch64_extract_operand()
[all …]
Dtic4x-dis.c606 const tic4x_inst_t *inst) in tic4x_hash_opcode_special() argument
612 && optable_special[i]->opcode == inst->opcode) in tic4x_hash_opcode_special()
615 optable_special[i] = (tic4x_inst_t *) inst; in tic4x_hash_opcode_special()
623 optable_special[i] = (tic4x_inst_t *) inst; in tic4x_hash_opcode_special()
638 const tic4x_inst_t *inst, in tic4x_hash_opcode() argument
642 int opcode = inst->opcode >> (32 - TIC4X_HASH_SIZE); in tic4x_hash_opcode()
643 int opmask = inst->opmask >> (32 - TIC4X_HASH_SIZE); in tic4x_hash_opcode()
650 && inst->oplevel & tic4x_oplevel) in tic4x_hash_opcode()
657 j, optable[j]->name, inst->name); in tic4x_hash_opcode()
664 && inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE))) in tic4x_hash_opcode()
[all …]
Daarch64-opc.h203 reset_operand_qualifier (aarch64_inst *inst, int idx) in reset_operand_qualifier() argument
205 assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode)); in reset_operand_qualifier()
206 inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL; in reset_operand_qualifier()
368 copy_operand_info (aarch64_inst *inst, int dst, int src) in copy_operand_info() argument
372 memcpy (&inst->operands[dst], &inst->operands[src], in copy_operand_info()
374 inst->operands[dst].idx = dst; in copy_operand_info()
Dm88k-dis.c577 unsigned long inst, in printop() argument
604 UEXT (inst, opptr->offset, opptr->width)); in printop()
609 UEXT (inst, opptr->offset, opptr->width)); in printop()
614 UEXT (inst, opptr->offset, opptr->width)); in printop()
619 UEXT (inst, opptr->offset, opptr->width)); in printop()
624 UEXT (inst, opptr->offset, opptr->width)); in printop()
628 extracted_field = UEXT (inst, opptr->offset, opptr->width); in printop()
636 extracted_field = UEXT (inst, opptr->offset, opptr->width); in printop()
641 extracted_field = UEXT (inst, opptr->offset, opptr->width); in printop()
660 (pc + (4 * (SEXT (inst, opptr->offset, opptr->width))), in printop()
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/
Dneon-vfp-reglist.s4 .macro ldnstn_reg_list type inst index rep
5 \inst\()1\rep {v0.\type}\index, [x0]
8 \inst\()1 {v0.\type, v1.\type}\index, [x0]
9 \inst\()1 {v0.\type, v1.\type, v2.\type}\index, [x0]
10 \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0]
14 \inst\()2\rep {v0.\type, v1.\type}\index, [x0]
16 \inst\()3\rep {v0.\type, v1.\type, v2.\type}\index, [x0]
18 \inst\()4\rep {v0.\type, v1.\type, v2.\type, v3.\type}\index, [x0]
25 ldnstn_reg_list type="8B", inst="ld" index="" rep=""
26 ldnstn_reg_list type="8B", inst="st" index="" rep=""
[all …]
Dneon-vfp-reglist-post.s9 .macro ldst1_reg_list_post_imm_64 inst type
10 \inst\()1 {v0.\type}, [x0], #8
11 \inst\()1 {v0.\type, v1.\type}, [x0], #16
12 \inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #24
13 \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
22 .macro ldst1_reg_list_post_imm_128 inst type
23 \inst\()1 {v0.\type}, [x0], #16
24 \inst\()1 {v0.\type, v1.\type}, [x0], #32
25 \inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #48
26 \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
[all …]
Dillegal.s242 .macro ldst2_reg_list_post_imm_reg_64 inst type postreg
243 \inst\()2 {v0.\type, v2.\type}, [x0], #16
244 \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
246 \inst\()2 {v0.\type, v2.\type}, [x0], \postreg
247 \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
251 .macro ldst2_reg_list_post_imm_reg_128 inst type postreg
252 \inst\()2 {v0.\type, v2.\type}, [x0], #32
253 \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
255 \inst\()2 {v0.\type, v2.\type}, [x0], \postreg
256 \inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
[all …]
/toolchain/binutils/binutils-2.25/gas/config/
Dtc-arm.c428 static struct arm_it inst; variable
828 return inst.cond != COND_ALWAYS; in conditional_insn()
842 inst.it_insn_type = type; \
851 inst.it_insn_type = type; \
860 if (inst.cond == COND_ALWAYS) \
966 inst.error = _("immediate expression requires a # prefix"); in my_get_expression()
992 if (inst.error == NULL) in my_get_expression()
993 inst.error = (ep->X_op == O_absent in my_get_expression()
1005 inst.error = _("bad segment"); in my_get_expression()
1024 inst.error = _("invalid constant"); in my_get_expression()
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Dtc-mcore.c856 unsigned short inst; in md_assemble() local
891 inst = opcode->inst; in md_assemble()
902 inst |= reg; in md_assemble()
908 inst |= reg; in md_assemble()
914 inst |= reg; in md_assemble()
920 output[0] = INST_BYTE0 (inst); in md_assemble()
921 output[1] = INST_BYTE1 (inst); in md_assemble()
932 inst |= reg; in md_assemble()
938 inst = MCORE_INST_BSR; /* With 0 displacement. */ in md_assemble()
939 output[0] = INST_BYTE0 (inst); in md_assemble()
[all …]
Dtc-microblaze.c893 unsigned long inst, inst1; in md_assemble() local
932 inst = opcode->bit_sequence; in md_assemble()
971 inst |= (reg1 << RD_LOW) & RD_MASK; in md_assemble()
972 inst |= (reg3 << RA_LOW) & RA_MASK; in md_assemble()
973 inst |= (reg2 << RB_LOW) & RB_MASK; in md_assemble()
977 inst |= (reg1 << RD_LOW) & RD_MASK; in md_assemble()
978 inst |= (reg2 << RA_LOW) & RA_MASK; in md_assemble()
979 inst |= (reg3 << RB_LOW) & RB_MASK; in md_assemble()
1063 inst = opcode->bit_sequence; in md_assemble()
1064 inst |= (reg1 << RD_LOW) & RD_MASK; in md_assemble()
[all …]
Dtc-aarch64.c136 static aarch64_instruction inst; variable
161 inst.parsing_error.kind = AARCH64_OPDE_NIL; in clear_error()
162 inst.parsing_error.error = NULL; in clear_error()
168 return inst.parsing_error.kind != AARCH64_OPDE_NIL; in error_p()
174 return inst.parsing_error.error; in get_error_message()
180 inst.parsing_error.error = error; in set_error_message()
186 return inst.parsing_error.kind; in get_error_kind()
192 inst.parsing_error.kind = kind; in set_error_kind()
198 inst.parsing_error.kind = kind; in set_error()
199 inst.parsing_error.error = error; in set_error()
[all …]
Dtc-tic4x.c131 tic4x_inst_t *inst; /* Pointer to first template. */ member
1218 tic4x_inst_insert (const tic4x_inst_t *inst) in tic4x_inst_insert() argument
1224 if (!strcmp (inst->name, prev_name) || inst->name[0] == '\0') in tic4x_inst_insert()
1227 retval = hash_insert (tic4x_op_hash, inst->name, (void *) inst); in tic4x_inst_insert()
1230 inst->name, retval); in tic4x_inst_insert()
1232 strcpy (prev_name, inst->name); in tic4x_inst_insert()
1292 tic4x_inst_t *inst; in tic4x_inst_add() local
1310 inst = tic4x_inst_make (name, insts[k].opcode + in tic4x_inst_add()
1315 ok &= tic4x_inst_insert (inst); in tic4x_inst_add()
1666 tic4x_operands_match (tic4x_inst_t *inst, tic4x_insn_t *tinsn, int check) in tic4x_operands_match() argument
[all …]
/toolchain/binutils/binutils-2.25/binutils/testsuite/binutils-all/aarch64/
Dunallocated-encoding.d10 0: 0d0047de .inst 0x0d0047de ; undefined
11 4: 0d2047dd .inst 0x0d2047dd ; undefined
12 8: 0d0067dc .inst 0x0d0067dc ; undefined
13 c: 0d2067db .inst 0x0d2067db ; undefined
14 10: 0d008bde .inst 0x0d008bde ; undefined
15 14: 0d208bdd .inst 0x0d208bdd ; undefined
16 18: 0d00abdc .inst 0x0d00abdc ; undefined
17 1c: 0d20abdb .inst 0x0d20abdb ; undefined
18 20: 0d008fde .inst 0x0d008fde ; undefined
19 24: 0d208fdd .inst 0x0d208fdd ; undefined
[all …]
Dunallocated-encoding.s5 .inst 0x0d0043de | (1 << 10)
7 .inst 0x0d2043dd | (1 << 10)
9 .inst 0x0d0063dc | (1 << 10)
11 .inst 0x0d2063db | (1 << 10)
15 .inst 0x0d0083de | (1 << 11)
17 .inst 0x0d2083dd | (1 << 11)
19 .inst 0x0d00a3dc | (1 << 11)
21 .inst 0x0d20a3db | (1 << 11)
25 .inst 0x0d0087de | (1 << 11)
27 .inst 0x0d2087dd | (1 << 11)
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Dvfma1.s6 .inst 0xee000a00 @ VFP vmla.f32 s0,s0,s0
7 .inst 0xee000b00 @ VFP vmla.f64 d0,d0,d0
8 .inst 0xf2000d10 @ NEON vmla.f32 d0,d0,d0
9 .inst 0xf2000d50 @ NEON vmla.f32 q0,q0,q0
12 .inst 0xeea00a00 @ VFP vfma.f32 s0,s0,s0
13 .inst 0xeea00b00 @ VFP vfma.f64 d0,d0,d0
14 .inst 0xf2000c10 @ NEON vfma.f32 d0,d0,d0
15 .inst 0xf2000c50 @ NEON vfma.f32 q0,q0,q0
18 .inst 0xee000a40 @ VFP vmls.F32 s0,s0,s0
19 .inst 0xee000b40 @ VFP vmls.F64 d0,d0,d0
[all …]
Dinst-po.s5 .inst 0x11a01009
12 .inst 0xbf0b + 1, 0x4649
13 .inst 0x4649
20 .inst.n 0xbf0b + 1, 0x4649, 0x4649
22 .inst.n 0x4649
26 .inst 0xea4f0109
27 .inst.w 0xea4f0109
Dinst-po-2.s7 .inst .L1
10 .inst.w 1
11 .inst.n 1
14 .inst 0xf000
15 .inst.n 1<<31
Dblx-bad.s12 .inst 0xf7ffeff6
13 .inst 0xf7ffeff5
15 .inst 0xf7ffeff1
16 .inst 0xf7ffeff0
Dinst-po-2.l5 [^:]*:14: Error: cannot determine Thumb instruction size. Use .inst.n/.inst.w instead
6 [^:]*:15: Error: .inst.n operand too big. Use .inst.w instead
Dinst-po-3.s9 .inst 0x4649
10 .inst 0x4649
17 .inst 0xbf0b + 1, 0x4649, 0x4649

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